MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 40

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Introduction
1-16
ANDI to CCR Source
ANDI to SR
ASL, ASR
BFEXTU
BFEXTS
Opcode
BFCHG
BFCLR
BFFFO
BFSET
BFTST
CAS2
CHK2
ADDQ
BCHG
BFINS
ABCD
ADDA
ADDX
BCLR
BKPT
BSET
BTST
CAS
ADDI
ANDI
CINV
ADD
AND
BRA
BSR
CHK
Bcc
8
2
2
BCD Source + BCD Destination + X ˘ Destination
Source + Destination ˘ Destination
Source + Destination ˘ Destination
Immediate Data + Destination ˘ Destination
Immediate Data + Destination ˘ Destination
Source + Destination + X ˘ Destination
Source
Immediate Data
If supervisor state
else TRAP
Destination Shifted by count ˘ Destination
If condition true
~(bit number of Destination) ˘ Z;
~(bit number of Destination) ˘ (bit number) of Destination
~(bit number of Destination) ˘ Z;
0 ˘ bit number of Destination
~(bit field of Destination) ˘ bit field of Destination
0 ˘ bit field of Destination
bit field of Source ˘ Dn
bit offset of Source ˘ Dn
bit offset of Source Bit Scan ˘ Dn
Dn ˘ bit field of Destination
1s ˘ bit field of Destination
bit field of Destination
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
PC + d n ˘ PC
~(bit number of Destination) ˘ Z;
1 ˘ bit number of Destination
SP – 4 ˘ SP; PC ˘ (SP); PC + d n ˘ PC
–(bit number of Destination) ˘ Z;
CAS Destination – Compare Operand ˘ cc;
if Z, Update Operand ˘ Destination
else Destination ˘ Compare Operand
CAS2 Destination 1 – Compare 1 ˘ cc;
if Z, Destination 2 – Compare ˘ cc;
if Z, Update 1 ˘ Destination 1;
else Destination 1 ˘ Compare 1;
If Dn < 0 or Dn > Source
If Rn < LB or If Rn > UB
If supervisor state
else TRAP
then Source
then PC + d n ˘ PC
Update 2 ˘ Destination 2
Destination 2 ˘ Compare 2
then TRAP
then TRAP
then invalidate selected cache lines
Destination ˘ Destination
CCR ˘ CCR
Table 1-3. Instruction Set Summary
Destination ˘ Destination
SR ˘ SR
Operation
M68060 USER’S MANUAL
ABCD Dy,Dx
ABCD –(Ay),–(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI #<data>,<ea>
ADDQ #<data>,<ea>
ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI #<data>,<ea>
ANDI #<data>,CCR
ANDI #<data>,SR
ASd Dx,Dy
ASd #<data>,Dy
ASd <ea>
Bcc <label>
BCHG Dn,<ea>
BCHG #<data>,<ea>
BCLR Dn,<ea>
BCLR #<data>,<ea>
BFEXTS <ea>{offset:width},Dn
BFEXTU <ea>{offset:width},Dn
BFFFO <ea>{offset:width},Dn
BKPT #<data>
BRA <label>
BSET Dn,<ea>
BSET #<data>,<ea>
BSR <label>
BTST Dn,<ea>
BTST #<data>,<ea>
CAS Dc,Du,<ea>
CAS2 Dc1–Dc2,Du1–Du2,(Rn1)–
(Rn2)
CHK <ea>,Dn
CHK2 <ea>,Rn
CINVL <caches>, (An)
CINVP <caches>, (An)
CINVA <caches>
BFCHG <ea>{offset:width}
BFCLR <ea>{offset:width}
BFINS Dn,<ea>{offset:width}
BFSET <ea>{offset:width}
BFTST <ea>{offset:width}
1
Syntax
MOTOROLA