DP83905AVQB National Semiconductor, DP83905AVQB Datasheet

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... AT LANTIC Controller’s ENDEC module and the twisted pair medium 1 0 System Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation AT LANTIC trademark of National Semiconductor Corporation PC- registered trademark of International Business Machines Corp ...

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General Description (Continued) The integrated ENDEC module allows Manchester encod- ing and decoding via a differential transceiver and phase lock Ioop decoder at 10 Mbit sec Also included are a colli- sion detect translator and diagnostic loopback capability The ENDEC ...

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... System Diagram (Continued CONNECTION DIAGRAM Order Number DP83905AVQB See NS Package Number VUL160A 11498– 2 ...

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Pin Description Pin No Pin Name Type ISA BUS INTERFACE PINS 94–97 SA0–SA1 9 I LATCHED ADDRESS BUS Low-order 20 bits of the system’s 24 bit address bus These lines are enabled onto the bus by the system ...

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Pin Description (Continued) Pin No Pin Name Type ISA BUS INTERFACE PINS (Continued) 123 CHRDY O OCH 122 AEN I TTL 89–92 INT0–3 O 3SH 61 DWID I MOS 93 lSACLK I TTL NETWORK INTERFACE PINS 156–153 TXOd ...

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Pin Description (Continued) Pin No Pin Name Type NETWORK INTERFACE PINS (Continued (OSCIN) I CRYSTAL OR EXTERNAL OSCILLATOR INPUT XTAL 8 X2 (OSCOUT) O CRYSTAL FEEDBACK OUTPUT Used in crystal connections only Should be left completely ...

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Pin Description (Continued) Pin No Pin Name Type EXTERNAL MEMORY SUPPORT (Continued) 36 RCS1 O RAM CHIP SELECT 1 Drives the chip select of the external RAM on the lower half of the memory support data bus MOS ...

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Simplified Application Diagram 4 0 Functional Description The AT LANTIC Controller is a highly integrated and config- urable Ethernet controller making it suitable for most Ether- net applications The AT LANTIC Controller integrates the functions of the following ...

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Functional Description FIGURE 1 Block Diagram of AT LANTIC Controller DETERMINING 8- OR 16-BIT WIDE DATA AT LANTIC Controller can treat the system data bus and all internal data busses bits wide 8- or ...

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Functional Description Shared Memory Compatible Mode I O Address Mapping The shared memory address decided by the Ad- dress Decode Register and the base I O address of AT LANTIC Controller is configured in Configuration ...

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Functional Description 16-BIT I O PORT COMPATIBLE MODE I O ADDRESS MAPPING This mode is compatible with Novell’s NE2000 The base I O address of the AT LANTIC Controller is configured by Configuration Register A (either upon power ...

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Functional Description line AT LANTIC Controller will not begin the next memory read until the previous word of data has been read On a remote write the system writes data to the I O port using an ‘‘OUTW’’ ...

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Functional Description 4 2 POWER ON RESET OPERATION The AT LANTIC Controller configures itself after a Reset signal is applied To be recognized as a valid Power-On-Re- set the Reset signal must be active for at least 415 ...

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Functional Description reads the next word in the EEPROM and appends this If in 8-bit mode it skips a word then reads and appends the next word Storing and Loading Configuration from EEPROM If the EECONFIG pin is ...

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Functional Description FIGURE 11 Example of Jumper Configuration Ethernet ID address (Configuration Register B bit 7 should be set to disable EEPROM configuration mode and Config- uration Register C bit 7 could be set to disable software configuration ...

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Functional Description at the desired base I O address If desired the configuration software could change the EEPROM content to the new values eliminating the need to reconfigure upon each power up Alternately the software could leave the ...

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Functional Description FIGURE 12 DP8390 Controller Core Simplified Block Diagram Transmit Serializer The Transmit Serializer reads parallel data from the FIFO and serializes it for transmission The serializer is clocked by the transmit clock generated internally The serial ...

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Functional Description For the case word threshold using a 20 MHz BSCLK tolerable latency ((13 10) 800 prevent a FIFO underrun a byte (or word) of data ...

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Functional Description 4 8 TWISTED PAIR INTERFACE MODULE The TPI consists of five main logical functions a) The Receiver Smart Squelch responsible for determin- ing when valid data is present on the differential receive inputs (RXI ) and ...

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Functional Description FIGURE 14 Twisted Pair Squelch Waveform The signal at the start of packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative depending upon polarity) will be ...

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Functional Description FIGURE 15 Typical Summed Transmit Waveform The signal with pre-emphasis shown above is generated by resistively combining TXO compliment is passed to the transmit filter FIGURE 16 External Circuitry to Connect AT LANTIC Controller to Twisted ...

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Functional Description FIGURE 17 Typical AT LANTIC Controller LED Connection FIGURE 18 Encoder Decode Block Diagram (Continued 11498– 11498 – 14 ...

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Functional Description Status Information Status information is provided by the AT LANTIC Controller on the RXLED TXLED COLED and POL outputs as de- scribed in the pin description table These outputs are suit- able for driving status LED’s ...

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Functional Description FIGURE 21 Connection from AT LANTIC Controller’s AUI Port to the AUI Connector clock signals and data The differential input must be exter- nally terminated with two 39 resistors connected in series if the standard 78 ...

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Register Descriptions 5 1 CONFIGURATION REGISTERS These registers are used to configure the operation of the AT LANTIC Controller typically after power up These registers control the configuration of bus interface setting options like interrupt selection I O ...

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Register Descriptions Mode Configuration Register B To prevent any accidental writes of this register it is ‘‘hidden’’ behind a previously unused register Register 0BH in the AT LANTIC Controller’s Page 0 of registers was previously reserved on a ...

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Register Descriptions Hardware Configuration Register C This register is configured during a RESET and can not be accessed by software 7 6 SOFEN CLKSEL Bits Symbols 0 –3 BPS0 3 BOOT PROM SELECT Selects address at which boot ...

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Register Descriptions 5 2 SHARED MEMORY MODE CONTROL REGISTERS The following tables describe the functionality of the two control registers and the 8 16 detection registers Shared Memory AT Detect Register (Read only Bits ...

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Register Descriptions (Continued NIC CORE REGISTERS All registers are 8-bit wide and mapped into two pages which are selected in the Command Register (PS0 PS1) Pins SA0 – SA3 are used to address registers within each ...

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Register Descriptions (Continued) Register Assignments Page 0 Address Assignments (PS1 SA0–SA3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 0 PS0 Command (CR) Command (CR) ...

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Register Descriptions (Continued) Page 1 Address Assignments (PS1 SA0–SA3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 0 PS0 Command (CR) Command (CR) Physical Address ...

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Register Descriptions (Continued) Page 2 Address Assignments (PS1 SA0–SA3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH OEH 0FH Note Page 2 registers should only be accessed for diagnostic purposes They should ...

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Register Descriptions COMMAND REGISTER (CR) 00H (READ WRITE) The Command Register is used to initiate transmissions enable or disable Remote DMA operations and to select register pages To issue a command the microprocessor sets the corresponding bit(s) (RD2 ...

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Register Descriptions INTERRUPT STATUS REGISTER (ISR) This register is accessed by the host processor to determine the cause of an interrupt Any interrupt can be masked in the Interrupt Mask Register (IMR) Individual interrupt bits are cleared by ...

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Register Descriptions INTERRUPT MASK REGISTER (IMR) The Interrupt Mask Register is used to mask interrupts Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR interrupt mask bit is set an interrupt ...

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Register Descriptions DATA CONFIGURATION REGISTER (DCR) This Register is used to program the AT LANTIC Controller for 8- or 16-bit memory interface select byte ordering in 16-bit applications and establish FIFO thresholds The DCR must be initialized prior ...

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Register Descriptions TRANSMIT CONFIGURATION REGISTER (TCR) The transmit configuration establishes the actions of the transmitter section of the AT LANTIC Controller during transmission of a packet on the network LB1 and LB0 which select Ioopback mode power up ...

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Register Descriptions (Continued) TRANSMIT STATUS REGISTER (TSR) This register records events that occur on the media during transmission of a packet It is cleared when the next transmission is initiated by the host All bits remain low unless ...

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Register Descriptions RECEIVE CONFIGURATION REGISTER (RCR) This register determines operation of the AT LANTIC Controller during reception of a packet and is used to program what types of packets to accept 7 6 Bits Symbols D0 SEP SAVE ...

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Register Descriptions RECEIVE STATUS REGISTER (RSR) This register records status of the received packet including information on errors and the type of address match either physical or multicast The contents of this register are written to buffer memory ...

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Register Descriptions (Continued) Note In the figure above registers are shown 16-bits wide Although some registers are 16-bit intemal registers all registers are accessed as 8-bit registers Thus the 16-bit Transmit Byte Count Register is ...

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Register Descriptions (Continued) the AT LANTIC Controller uses fixed 256-byte buffers aligned on page boundaries only the upper eight bits of the start and stop address are specified PSTART PSTOP bit assignment PSTART ...

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Register Descriptions (Continued) bits to set in the multicast registers All multicast filter bits that correspond to multicast address accepted by the node are then set to one To accept all multicast packets all of the registers are ...

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Operation of AT LANTIC Controller the CRC generator Packets with improper CRC will be re jected The AUTODlN ...

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Operation of AT LANTIC Controller FIGURE 28 AT LANTIC Controller Receiver Buffer Ring 6 3 PACKET RECEPTION The Local DMA receive channel uses a Buffer Ring Struc- ture comprised of a series of contiguous fixed length 256 byte ...

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Operation of AT LANTIC Controller Ring not yet read by the host If the local DMA address ever reaches the Boundary reception is aborted The Boundary Pointer is also used to initialize the Remote DMA for remov- ing ...

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Operation of AT LANTIC Controller 4 Clear the AT LANTIC Controller’s Remote Byte Count registers (RBCR0 and RBCR1) 5 Read the stored value of the TXP bit from step 1 above If this value set ...

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Operation of AT LANTIC Controller FIGURE 33 Received Packet Aborted if it Hits Boundary Enabling the AT LANTIC Controller on an Active Network After the AT LANTIC Controller has been initialized the pro- cedure for disabling and then ...

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Operation of AT LANTIC Controller Error Recovery If the packet is rejected as shown the DMA is restored by the AT LANTIC Controller by reprogramming the DMA starting address pointed to by the Current Page Register Storage Format ...

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Operation of AT LANTIC Controller Transmit Packet Assembly Format The following diagrams describe the format for how packets must be assembled prior to transmission for different byte ordering schemes The various formats are selected in the Data Configuration ...

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Operation of AT LANTIC Controller When in word-wide mode with Byte Order Select low the following format must be used for the loopback packet Note When using loopback in word mode 2n bytes must be programmed in the ...

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Operation of AT LANTIC Controller loopback testing When loopback mode is selected in the TCR the FIFO is spilt A packet should be assembled in memory with programming of TPSR and TBCR0 TBCR1 registers When the transmit command ...

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Operation of AT LANTIC Controller FIGURE 36 Tally Counters Network Management Functions Network management capabilities are required for mainte- nance and planning of a local area network AT LANTIC Controller supports the minimum requirement for network management in ...

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Operation of AT LANTIC Controller FIGURE Operation All Data Transfers and Arbitration is Controlled by the NIC Core INTERLEAVED LOCAL REMOTE OPERATION When mode the remote DMA is used to transfer data ...

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Operation of AT LANTIC Controller FIGURE 40 Remote DMA Autoinitialization from Buffer Ring I O MODE REMOTE DMA COMMANDS The Remote DMA channel is used in the I O Mode to both assemble packets for transmission and to ...

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Operation of AT LANTIC Controller Steps 1–3 are repeated until the remote DMA is complete (i e the byte count has gone to zero) Note that in order for the Remote DMA to transfer a word from memory ...

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Operation of AT LANTIC Controller This is the type of cycle used to read from a register or in 8-bit I O mode from a data transfer port These accesses are entirely asynchronous with the AT LANTIC Controller ...

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Operation of AT LANTIC Controller This is the type of cycle used to read from a data transfer port in 16-bit I O mode These accesses are entirely asynchronous with the AT LANTIC Controller responding when it decodes ...

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Operation of AT LANTIC Controller Some Chips and Technologies and VLSI Technologies PC-AT chip sets have timing requirements in 16-bit I O cycles that cannot be achieved by the default AT LANTIC cycle described on the previous page ...

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Operation of AT LANTIC Controller ISA Bus Shared Memory Access Timing Shared Memory Mode Read Bus Timing with DWID Low This is the type of cycle used to read from buffer RAM in shared memory mode when DWlD ...

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Operation of AT LANTIC Controller Shared Memory Mode Write Bus Timing with DWID Low This is the type of cycle used to write to buffer RAM in shared memory mode when DWlD is low These accesses are entirely ...

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Operation of AT LANTIC Controller 16-Bit Shared Memory Mode Read Bus Timing with DWID High This is the type of cycle used to read 16 bits from buffer RAM is shared memory mode when DWID is high These ...

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Operation of AT LANTIC Controller 16-Bit Shared Memory Mode Write Bus Timing with DWID High This is the type of cycle used to write 16 bits to buffer RAM in shared memory mode when DWID is high These ...

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Operation of AT LANTIC Controller 8-Bit Shared Memory Mode Read Bus Timing with DWID High This is the type of cycle used to read 8 bits from buffer RAM in shared memory mode when DWID is high These ...

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Operation of AT LANTIC Controller 8-Bit Shared Memory Mode Write Bus Timing with DWID High This is the type of cycle used to write 8 bits to buffer RAM in shared memory mode when DWID is high These ...

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Operation of AT LANTIC Controller ISA Bus Boot PROM Access Timing This is the type of cycle used to read the boot PROM These accesses are entirely asynchronous with the AT LANTIC Controller responding when it decodes the ...

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Operation of AT LANTIC Controller This is the type of cycle used to write to the boot PROM These accesses are entirely asynchronous with the AT LANTIC Controller responding when it decodes the correct address on SA0– 19 ...

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Operation of AT LANTIC Controller RAM Access Timing This is a memory read cycle executed by the AT LANTIC Controller’s internal DMA This is used to either load the data transfer port during a Remote Read in I ...

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... Preliminary Electrical Characteristics Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Storage Temperature (T ) STG Package Power Dissipation ( Lead Temperature ( (Soldering 10 seconds) Preliminary DC Specifications Symbol Description ...

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Preliminary Electrical Characteristics Preliminary DC Specifications Symbol Description OCH OPEN COLLECTOR HIGH DRIVE OUTPUT V Maximum Low Level Output Voltage OL LED DRIVER OUTPUT V Maximum Low Level Output Voltage OL THIN DRIVER OUTPUT V Minimum High Level ...

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Preliminary Switching Characteristics Memory Support Bus Accesses (for I O port or FIFO transfers) Symbol Description T1 MSA1 15 Valid before RCS b Asserted (Note 1) T2 MSA1 15 Valid before b MSRD WR Asserted b T3 MSRD ...

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Preliminary Switching Characteristics (Continued) ISA Slave Accesses 11498 – 54 ...

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Preliminary Switching Characteristics ISA Slave Accesses Symbol Description T1 BALE Width T2 AEN Valid before Command Strobe Active T3a SBHE and SA0–9 Valid before IORD IOWR Asserted T3b SA0–9 Valid before MRD MWR Asserted T4a IORD MRD Asserted ...

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Preliminary Switching Characteristics ISA Slave Accesses Symbol Description T22 BALE Deasserted before LA17–23 Invalid T23 LA17–23 Valid before MRD MWR Asserted T24 Read Data Valid on MSD0–15 to Valid on SD0–15 T25 MSRD Deasserted to MSD0–15 Read Data ...

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Preliminary Switching Characteristics RESET Timing Symbol T1 RESET Asserted Until IO Inactive Asserted (Note 1) T2 RESET Asserted Until RegLoad State Entered (Note 2) T3 RESET Deasserted Until RegLoad Deasserted (Note 3) T4 RESET Deasserted Until EELOAD State ...

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Preliminary Switching Characteristics AUI Transmit Timing (End of Packet) Symbol Description t Transmit Output High before Idle TOh t Transmit Output Idle Time TOI AUI TPI Receive Timing (End of Packet) Symbol t Receive End of Packet Hold ...

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Preliminary Switching Characteristics Link Pulse Timing Symbol Description t Time between Link Output Pulses Ip t Link Integrity Output Pulse Width Ipw (Continued) Min Max 130 11498 – 59 Units ns ns ...

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Preliminary Switching Characteristics TPI Transmit Timing (End of Packet) Symbol Description t Pre-Emphasis Output Delay (TXO del t Transmit Hold Time at End of Packet (TXO Off t Transmit Hold Time at End of Packet (TXOd Offd Note ...

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AC Timing Test Conditions Input Pulse Levels (TTL CMOS) Input Rise and Fall Times (TTL CMOS) Input and Output Reference Levels (TTL CMOS) Input Pulse Levels (Diff ) 350 Input and Output Reference Levels (Diff ...

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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Quad Flat Package (VUL) Order Number DP83905AVQB NS Package Number VUL160A ...