DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 52

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

6 0 Operation of AT LANTIC Controller
loopback testing When loopback mode is selected in the
TCR the FIFO is spilt A packet should be assembled in
memory with programming of TPSR and TBCR0 TBCR1
registers When the transmit command is issued the follow-
ing operations occur
TRANSMITTER ACTIONS
1 Data is transferred from memory by the DMA until the
2 The AT LANTIC Controller generates 56 bits of pream-
3 Data transferred from FIFO to serializer
4 If CRC
5 At end of Transmission PTX bit set in ISR
RECEIVER ACTIONS
1 Wait for synch all preamble stripped
2 Store packet in FIFO increment receive byte count for
3 If CRC
4 At end of receive receive byte count written into FIFO
EXAMPLES
The following examples show what results can be expected
from a properly operating AT LANTIC Controller during
loopback The restrictions and results of each type of Ioop-
back are listed for reference The loopback tests are divided
into two sets of tests One to verify the data path CRC
generation and byte count through all three paths The sec-
ond set of tests uses internal loopback to verify the receiv-
er’s CRC checking and address recognition For all of the
tests the DCR was programmed to 40H
Note 1 Since carrier sense and collision detect are generated in the
Note 2 CRC errors are always indicated by receiver if CRC is appended by
Note 3 Only the PTX bit in the ISR is set the PRX bit is only set if status is
Note 4 All values are hex
AT LANTIC
Controller
FIFO is filled For each transfer TBCR0 and TBCR1 are
decremented (Subsequent burst transfers are initiated
when the number of bytes in the FIFO drops below the
programmed threshold )
ble followed by an 8-bit synch pattern
Controller the last byte transmitted is the last byte from
the FIFO (allows software CRC to be appended) If
CRC
pends four bytes of CRC
each incoming byte
CRC errors If CRC
CRC errors CRC error bit always set in RSR (for address
matching packets)
receive status register is updated The PRX bit is typically
set in the RSR even if the address does not match If
CRC errors are forced the packet must match the ad-
dress filters in order for the CRC error bit in the RS to be
set
Internal
Path
ENDEC module They are blocked during internal loopback carrier
and CD heartbeat are not seen and the CRS and CDH bits are set
the transmitter
written to memory In loopback this action does not occur and the
PRx bit remains 0 for all loopback modes
e
e
e
0 AT LANTIC Controller calculates and ap-
0 in TRC receiver checks incoming packet for
1 in TCR no CRC calculated by AT LANTIC
TCR RCR
02
e
1F
1 in TCR receiver does not check
(Note 1) (Note 2) (Note 3)
TSR
53
RSR
02
ISR
02
52
(Continued)
Note 1 CDH is set CRS is not set since it is generated by the external
Note 1 CDH and CRS should not be set The TSR however could also
Note 2 Will contain 08H if packet is not transmittable
Note 3 During extemal loopback the AT LANTIC Controller is now ex-
Note 4 All values are hex
CRC and Address Recognition
The next three tests exercise the address recognition logic
and CRC These tests should be performed using internal
Ioopback only so that the AT LANTIC Controller is isolated
from interference from the network These tests also require
the capability to generate CRC in software
The address recognition logic cannot be directly tested The
CRC and FAE bits in the RSR are only set if the address in
the packet matches the address filters If errors are expect-
ed to be set and they are not set the packet has been
rejected on the basis of an address mismatch The following
sequence of packets will test the address recognition logic
The DCR should be set to 40H the TCR should be set to
03H with a software generated CRC
Note 1 Status will read 21H if multicast address used
Note 2 Status will read 22H if multicast address used
Note 3 In test A the RSR is set up In test B the address is found to match
Note 4 All values are hex
AT LANTIC
AT LANTIC
Controller
Test A
Test B
Test C
Controller
External
Test
Internal
Path
Path
Packet Contents
encoder decoder
contain 01H 03H 07H and a variety of other values depending on
whether collisions were encountered or the packet was deferred
posed to network traffic it is therefore possible for the contents of
both the Receive portion of the FIFO and the RSR to be corrupted
by any other packet on the network Thus in a live network the
contents of the FIFO and RSR should not be depended on The
AT LANTIC Controller will still abide by the standard CSMA CD
protocol in external loopback mode (i e the network will not be
disturbed by the loopback packet)
since the CRC is flagged as bad Test C proves that the address
recognition logic can distinguish a bad address and does not notify
the RSR of the bad CRC The receiving CRC is proven to work in
test A and test B
Non-Matching
TCR RCR
Matching
Matching
Address
TCR
06
04
1F
RCR
1F
(Note 1)
TSR
(Note 1)
03
Good
CRC
Bad
Bad
TSR
43
Results
RSR
02
01 (Note 1)
02 (Note 2)
RSR
02
RSR
(Note 2)
01
ISR
02
ISR
02