DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 9

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

4 0 Functional Description
DETERMINING 8- OR 16-BIT WIDE DATA
AT LANTIC Controller can treat the system data bus and all
internal data busses as 8 or 16 bits wide 8- or 16-bit mode
is determined by the DWlD pin For an adapter card this bit
can be used to automatically detect if the card has been
plugged into an 8- or 16-bit slot If this pin is connected to a
V
into a 16-bit slot enabling 16-bit mode and floating when
plugged into an 8-bit slot When floating the internal pull-
down resistor will enable 8-bit mode
SHARED MEMORY ARCHITECTURE
DD
on the upper connector it will be high when plugged
FIGURE 2 Shared Memory
FIGURE 1 Block Diagram of AT LANTIC Controller
(Continued)
TL F 11498 – 5
9
In this mode the AT LANTIC Controller’s internal memory
map using external RAM devices is mapped into the host
system’s memory map Both the AT LANTIC Controller and
the host system can directly access this memory The
AT LANTIC Controller controls the arbitration for this mem-
ory area giving priority to its internal accesses It also has
an internal FIFO to allow for any latency on internal trans-
fers introduced by system accesses If a system access oc-
curs while an internal access is current the AT LANTIC
Controller will insert wait states into the system cycle until
the internal transfer is complete
In this mode the AT LANTIC Controller’s internal registers
are accessed within the system’s I O map The address
within this I O map is set by Configuration Register A The
user programs the address of the shared memory within the
host systems memory map by writing to a register in
AT LANTIC Controller The memory is not accessible by
the user until after this register has been programmed
There are two basic Shared Memory modes compatible
mode and non-compatible mode as described in the fol-
lowing text
TL F 11498 – 4