DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 42

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

5 0 Register Descriptions
the AT LANTIC Controller uses fixed 256-byte buffers
aligned on page boundaries only the upper eight bits of the
start and stop address are specified
PSTART PSTOP bit assignment
BOUNDARY (BNRY) REGISTER
This register is used to prevent overflow of the Receive
Buffer Ring Buffer management compares the contents of
this register to the next buffer address when linking buffers
together If the contents of this register match the next buff-
er address the Local DMA operation is aborted
CURRENT PAGE REGISTER (CURR)
This register is used internally by the Buffer Management
Logic as a backup register for reception CURR contains the
address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive
errors This register is initialized to the same value as
PSTART and should not be written to again unless the con-
troller is Reset
CURRENT LOCAL DMA REGISTER 0 1 (CLDA0 1)
These two registers can be accessed to determine the cur-
rent Local DMA Address
Remote DMA Registers
REMOTE START ADDRESS REGISTERS (RSAR0 1)
Remote DMA operations are programmed via the Remote
Start Address (RSAR0 1) and Remote Byte Count
(RBCR0 1) registers The Remote Start Address is used to
point to the start of the block of data to be transferred and
the Remote Byte Count is used to indicate the length of the
block (in bytes)
PSTART
BNRY
CURR
CLDA1
CLDA0
RSAR1
RSAR0
PSTOP
A15
A15
A15
A15
7
A7
7
A7
A15
7
7
7
7
7
A14
A14
A14
A14
A6
6
6
A6
A14
6
6
6
6
6
A13
A13
A13
A13
A5
5
A5
A13
5
5
5
5
5
5
A12
A12
A12
A12
A4
A12
4
A4
4
4
4
4
4
4
A11
A11
A11
A11
A11
A3
A3
3
3
3
3
3
3
3
(Continued)
A10
A10
A10
A10
A10
A2
A2
2
2
2
2
2
2
2
A9
A9
A9
A1
A9
A1
A9
1
1
1
1
1
1
1
A8
A8
A8
A0
A8
A8
A0
0
0
0
0
0
0
0
42
REMOTE BYTE COUNT REGISTERS (RCB0 1)
Notes
RSAR0 programs the start address bits A0–A7
RSAR1 programs the start address bits A8–A15
Address incremented by two for word transfers and by one for byte trans-
fers Byte count decremented by two for word transfers and by one for byte
transfers
RBCR0 programs LSB byte count
RBCR1 programs MSB byte count
CURRENT REMOTE DMA ADDRESS (CRDA0 CRDA1)
The Current Remote DMA Registers contain the current ad-
dress of the Remote DMA The bit assignment is shown
below
Physical Address Registers (PAR0– PAR5)
The physical address registers are used to compare the
destination address of incoming packets for rejecting or ac-
cepting packets Comparisons are performed on a byte-
wide basis The bit assignment shown below relates the se-
quence in PAR0– PAR5 to the bit sequence of the received
packet
Note P S
Multicast Address Registers (MAR0– MAR7)
The multicast address registers provide filtering of multicast
addresses hashed by the CRC logic All destination ad-
dresses are fed through the CRC logic and as the last bit of
the destination address enters the CRC the 6 most signifi-
cant bits of the CRC generator are latched These 6 bits are
then decoded by a 1 of 64 decode to index a unique filter bit
(FB0– 63) in the multicast address registers If the filter bit
selected is set the multicast packet is accepted The sys-
tem designer would use a program to determine which filter
PARC DA31 DA30 DA29 DA28 DA27 DA26 DA25 DA24
PAR0 DA7
PAR1 DA15 DA14 DA13 DA12 DA11 DA10 DA9
PAR2 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16
PAR4 DA39 DA38 DA37 DA36 DA35 DA34 DA33 DA32
PAR5 DA47 DA46 DA45 DA44 DA43 DA42 DA41 DA40
P S DA0 DA1 DA2 DA3
RBCR1
RBCR0
CRDA1
CRDA0
DA0
Destination Address
D7
e
e
A15
A15
Preamble Synch
Physical Multicast Bit
A7
A7
7
7
7
7
DA6
D6
A14
A14
A6
A6
6
6
6
6
DA5
D5
A13
A13
A5
A5
5
5
5
5
DA4
D4
A12
A12
A4
A4
4
4
4
4
DA3
DA46 DA47 SA0
D3
A11
A11
A3
A3
3
3
3
3
DA2
D2
A10
A10
A2
A2
2
2
2
2
Source
DA1
D1
A9
A1
A9
A1
1
1
1
1
DA0
DA8
D0
A8
A0
A8
A0
0
0
0
0