DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 36

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

D5 and D6
5 0 Register Descriptions
DATA CONFIGURATION REGISTER (DCR)
This Register is used to program the AT LANTIC Controller for 8- or 16-bit memory interface select byte ordering in 16-bit
applications and establish FIFO thresholds The DCR must be initialized prior to loading the Remote Byte Count Registers
LAS is set on power up
Bits
D0
D1
D2
D3
D4
WTS
BOS
LAS
LS
ARM
FT0 and FT1
Symbols
7
WORD TRANSFER SELECT
Note When word-wide mode is selected up to 32k words are addressable A0 remains low
BYTE ORDER SELECT
LONG ADDRESS SELECT
LOOPBACK SELECT
AUTO-INITIALIZE REMOTE
Note Send Command cannot be used with 680x0 byte processors
FlFO THRESHOLD SELECT Encoded FIFO threshold Establishes point at which the
memory bus is requested when filling or emptying the FIFO During reception the FIFO
threshold indicates the number of bytes (or words) the FIFO has filled serially from the
network before the FIFO is emptied onto the memory bus
Note FIFO threshold setting determines the DMA burst length
FT1
During transmission the FIFO threshold indicates the number of bytes (or words) the FIFO
has filled from the Local DMA before being transferred to the memory Thus the transmission
threshold is 13 bytes less the received threshold
0
0
1
1
0 Selects byte-wide DMA transfers
1 Selects word-wide DMA transfers
0 MS byte placed on AD15–AD8 and LS byte on AD7–AD0 (32xxx 80x86)
1 MS byte placed on AD7–AD0 and LS byte on AD15–AD8 (680x0)
0 Dual 16-bit DMA mode
1 Single 32-bit DMA mode
as A16–A31 Power up high
0 Loopback mode selected Bits D1 and D2 of the TCR must also be programmed for
1 Normal Operation
0 Send Command not executed all packets removed from Buffer Ring under
1 Send Command executed Remote DMA auto-initialized to remove packets from
Receive Thresholds
FT1
WTS establishes byte or word transfers for both Remote and Local DMA transfers
Ignored when WTS is low
When LAS is high the contents of the Remote DMA registers RSAR0 1 are issued
6
Loopback operation
program control
Buffer Ring
FT0
0
1
0
1
(Continued)
FT0
5
0EH (WRITE)
Word Wide
2 Words
4 Words
6 Words
1 Word
ARM
4
36
LS
3
Byte Wide
2 Bytes
4 Bytes
8 Bytes
12 Bytes
Description
LAS
2
BOS
1
WTS
0