DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 7

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

EXTERNAL MEMORY SUPPORT
LOW POWER SUPPORT
TEST SUPPORT
POWER SUPPLY PINS
36
34
38
39
12
62
11
160
159
157 152
144 143
139
158 149
140 138
9
6
59 49
24 13
60 54 44
35 23 14
132 121
107 87 68
135 129
125 124
116 98
85 71 65
2 0 Pin Description
Attachment Unit Interface TPI
Pin No
Driver Types are I
RCS1
RCS2
EECS
EECONFIG
BSCLK
LOWPWR
TEST
PLLV
PLLGND
PV
PGND
OV
OGND
V
GND
IFV
lFGND
Pin Name
CC
CC
CC
e
CC
CC
Input O
e
e
Twisted Pair Interface LED
Type
Output I O
MOS
MOS
MOS
MOS
TTL
TTL
TTL
O
O
O
I
I
I
I
(Continued)
(Continued)
RAM CHIP SELECT 1 Drives the chip select of the external RAM on the lower half
of the memory support data bus
RAM CHIP SELECT 2 Drives the chip select of the external RAM on the upper half
of the memory support data bus
EEPROM CHIP SELECT Strobes data from the EEPROM onto the memory support
data bus
CONFIGURE FROM EEPROM When this pin is tied high the AT LANTIC Controller
loads the configuration from an EEPROM
INTERNAL BUS CLOCK This controls the speed of the NIC core if it is not running
off of an internal clock (see Configuration Register C) This pin should be tied to
ground if it is unused
LOW POWER Instructs AT LANTIC Controller to enter its low power mode as
detailed in Section 4 5 Should be tied to ground for normal operation
TEST This input is only used for test mode It should be left unconnected as it has
an internal pull-down resistor which will enable correct operation
PLL 5V SUPPLY PINS This pin supplies 5V to the AT LANTIC’s analog PLL inside
the ENDEC block To maximize data recovery it is recommended that analog layout
and decoupling rules be applied between this pin and PLLGND
PLL NEGATIVE (GROUND) SUPPLY PINS
PHYSICAL MEDIA 5V SUPPLY PINS These pins supply 5V to the AT LANTIC’s
analog physical media interface circuitry
PHYSICAL LAYER NEGATIVE (GROUND) SUPPLY PINS These pins are the
ground to the AT LANTIC’s analog physical media interface circuitry
OSClLLATOR 5V SUPPLY PINS This pin supplies 5V to the AT LANTIC’s oscillator
and LED circuitry
OSCILLATOR NEGATIVE (GROUND) SUPPLY PINS This pin is the ground to the
AT LANTIC’s oscillator and LED circuitry
POSITIVE 5V SUPPLY PINS These pins supply power to the AT LANTIC
Controller’s logic
NEGATIVE (GROUND) SUPPLY PINS These are the supply pins for the
AT LANTIC Controller’s logic It is suggested that decoupling capacitors be
connected between the V
for the GND pins with the lowest possible impedance
INTERFACE POSITIVE 5V SUPPLY PINS These pins supply power to the
AT LANTIC Controller’s ISA interface
INTERFACE NEGATIVE (GROUND) SUPPLY PINS These are the supply pins for
the AT LANTIC Controller’s ISA interface It is suggested that decoupling capacitors
be connected between the IFV
ground for the IFGND pins with the lowest possible impedance
e
Bi-directional Output OCH
e
LED Drive MOS
e
7
Open Collector 3SH
CC
e
CMOS Level Compatible XTAL
and GND pins It is essential to provide a path to ground
CC
and IFGND pins It is essential to provide a path to
Description
e
TRI-STATE Output TTL
e
Crystal
e
TTL Compatible AUI
e