DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 35
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DP83905AVQB
Manufacturer Part Number
DP83905AVQB
Description
IC CONTROLR AT/LAN TP IN 160PQFP
Manufacturer
National Semiconductor
Series
AT/LANTIC™r
Datasheet
1.DP83905AVQB.pdf
(80 pages)
Specifications of DP83905AVQB
Controller Type
AT, LAN Twisted-Pair Interface Controller
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
100mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Interface
-
Other names
*DP83905AVQB
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83905AVQB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83905AVQB
Manufacturer:
NS/国半
Quantity:
20 000
Bits
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Register Descriptions
INTERRUPT MASK REGISTER (IMR)
The Interrupt Mask Register is used to mask interrupts Each interrupt mask bit corresponds to a bit in the Interrupt Status
Register (ISR) If an interrupt mask bit is set an interrupt will be issued whenever the corresponding bit in the ISR is set If any bit
in the IMR is set low an interrupt will not occur when the bit in the ISR is set The IMR powers up all zeros
Symbols
PRXE
PTXE
RXEE
TXEE
OVWE
CNTE
RDCE
reserved
PACKET RECEIVED INTERRUPT ENABLE
PACKET TRANSMITTED INTERRUPT ENABLE
RECEIVE ERROR INTERRUPT ENABLE
TRANSMIT ERROR INTERRUPT ENABLE
OVERWRITE WARNING INTERRUPT ENABLE
COUNTER OVERFLOW INTERRUPT ENABLE
DMA COMPLETE INTERRUPT ENABLE
reserved
0 Interrupt Disabled
1 Enables Interrupt when packet received
0 Interrupt Disabled
1 Enables Interrupt when packet is transmitted
0 Interrupt Disabled
1 Enables Interrupt when packet received with error
0 Interrupt Disabled
1 Enables Interrupt when packet transmission results in error
0 Interrupt Disabled
1 Enables Interrupt when Buffer Management Logic lacks sufficient buffers to store incoming packet
0 Interrupt Disabled
1 Enables Interrupt when MSB of one or more of the Network Statistics counters has been set
0 Interrupt Disabled
1 Enables Interrupt when Remote DMA transfer has been completed
7
RDCE
6
CNTE
(Continued)
5
0FH (WRITE)
OVWE
4
35
TXEE
Description
3
RXEE
2
PTXE
1
PRXE
0