VSC8601XKN Vitesse Semiconductor Corp, VSC8601XKN Datasheet - Page 25
![IC PHY 10/100/1000 64-EP-LQFP](/photos/6/86/68666/64-lqfp_exposed_pad__64-elqfp__64-hlqfp_sml.jpg)
VSC8601XKN
Manufacturer Part Number
VSC8601XKN
Description
IC PHY 10/100/1000 64-EP-LQFP
Manufacturer
Vitesse Semiconductor Corp
Type
PHY Transceiverr
Specifications of VSC8601XKN
Number Of Drivers/receivers
1/1
Protocol
Gigabit Ethernet
Voltage - Supply
2.5V, 3.3V
Mounting Type
Surface Mount
Package / Case
64-LQFP Exposed Pad, 64-eLQFP, 64-HLQFP
Case
TQFP
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
907-1028
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
VSC8601XKN
Manufacturer:
KYOCERA/AVX
Quantity:
20 000
Company:
Part Number:
VSC8601XKN
Manufacturer:
VITESSE
Quantity:
1 235
Company:
Part Number:
VSC8601XKN
Manufacturer:
Vitesse Semiconductor Corporation
Quantity:
10 000
Part Number:
VSC8601XKN
Manufacturer:
VITESSE
Quantity:
20 000
3.10.2
3.10.3
3.11
3.11.1
Revision 4.1
September 2009
Link Partner Wake-Up State
In this state, the PHY attempts to wake up the link partner. FLP bursts are sent on
alternating pairs A and B of the Cat5 media for a duration of two seconds.
In this state, the following functionality is provided:
•
•
After sending signal energy on the relevant media, the PHY returns to the low-power
state.
Normal Operating State
In this state, the PHY establishes a link with a link partner. When the media is
unplugged or the link partner is powered down, the PHY waits for the duration of the
programmable link status time-out timer, which is set using register bit 28.7 and
bit 28.2. It then enters the low-power state.
Serial Management Interface
The VSC8601 device includes an IEEE 802.3-compliant serial management interface
(SMI) that is affected by use of its MDC and MDIO pins. The SMI provides access to
device control and status registers. The register set that controls the SMI consists of 32
16-bit registers, including all required IEEE-specified registers. Also, there are
additional pages of registers accessible by means of device register 31.
For more information, see
The SMI is a synchronous serial interface with bidirectional data on the MDIO pin that is
clocked on the rising edge of the MDC pin. The interface can be clocked at a rate from
0 MHz to 25 MHz, depending upon the total load on MDIO. An external, 2 kΩ pull-up
resistor is required on the MDIO pin.
SMI Frames
Data is transferred over the SMI using 32-bit frames with an optional and arbitrary
length preamble. The following illustrations show the SMI frame format for the read
operation and write operation.
SMI interface (MDC, MDIO, MDINT)
CLKOUT
“Extended Page Registers,”
page 55.
Functional Descriptions
VSC8601 Datasheet
Page 25