VSC8601XKN Vitesse Semiconductor Corp, VSC8601XKN Datasheet - Page 64

• Manufacturer Part Number: VSC8601XKN
• Description: IC PHY 10/100/1000 64-EP-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8601XKN

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP Exposed Pad, 64-eLQFP, 64-HLQFP
• Case: TQFP
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1028

4.3.14
Table 48.
4.4
4.4.1
Table 49.
Revision 4.1
September 2009
CMODE Pin Bit 3 (MSB) Control Bit 2 Controls
3
2
1
0
PHY address [3]
PHY address [2]
PHY address [1]
PHY address [0]
Ethernet Packet Generator Control 2
The register at address 30E consists of the second of bits that provide access to and
control over various aspects of the EPG testing feature. For information about the first
set of EPG control bits, see
available.
EPG Control Register 2, Address 30E (0x1E)
Note If any of bits 15:0 in this register are changed while the EPG is running (bit 14
of register 29E is set to 1), that bit (29E.14) must first be cleared and then set back to
1 for the change to take effect and to restart the EPG.
CMODE
The information in this section consists of a detailed description of the methods to
configure the VSC8601 device using its CMODE pins. It includes descriptions of the
registers that work together with the CMODE pins to control the device function.
There are four configuration mode (CMODE) pins on the VSC8601 device. For more
information about the physical location of the CMODE pins, see
page 84. Each CMODE pin maps to a configuration bit, which means there are 16
possible settings for the device.
CMODE Pins and Related Functions
The following table lists the pin numbers and device functionality that is controlled by
each configuration bit.
CMODE Configuration Pins and Device Functions
Bit
15:0
Name
EPG packet payload
ActiPHY
Link speed downshift
PHY address [4]
CLKOUT enable
Table 47,
Access
R/W
Description
Data pattern repeated in the payload of
packets generated by the EPG
page 63. The following table lists the settings
Bit 1 Controls
MAC calibration
setting[1]
RGMII clock skew[1]
Speed/Duplex Modes
[1]
Advertise asymmetric
pause
“Pin Descriptions,”
MAC calibration
setting[0]
RGMII clock skew[0]
Speed/Duplex modes [0]
Advertise symmetric
pause
Bit 0 (LSB) Controls
VSC8601 Datasheet
Configuration
Default
0x00
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