VSC8601XKN Vitesse Semiconductor Corp, VSC8601XKN Datasheet - Page 96

• Manufacturer Part Number: VSC8601XKN
• Description: IC PHY 10/100/1000 64-EP-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8601XKN

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP Exposed Pad, 64-eLQFP, 64-HLQFP
• Case: TQFP
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1028

8
8.1
8.2
8.3
Revision 4.1
September 2009
Design Considerations
This section explains various issues associated with the VSC8601 device.
RX_CLK Can Reach as High as 55% Duty Cycle
Issue: When register 23, bit 8 = 0 (no internal clock skew) for RGMII, then the RX_CLK
duty cycle has been measured as high as 55%.
Implications: There is a possibility that the duty cycle can go beyond this value, which
then violates what is specified in the datasheet. This has only been observed when the
skew setting is set to 0.
Workaround: Avoid using an RGMII skew setting of 0.
First SMI Write Fails after Software Reset
Issue: After applying software reset (using either register 0, bit 15 or the NSRESET
pin), the first subsequent SMI write operation into register 4 (auto-negotiation
advertisement) or register 9 (1000BASE-T control) does not work. This issue only
occurs if the first SMI write after software reset is into register 4 or 9. This issue does
not occur if any kind of SMI transaction (either read or write) is applied to any register
between the time of the software reset and the SMI write into register 4 or 9.
Implications: The PHY may operate unexpectedly, because settings for registers 4
and 9 remain at the reset value. There are no such implications after either hardware
reset or power-down events.
Workaround: Writing “0x0000” into register 31 after every software reset avoids this
issue, and subsequent SMI writes into register 4 or 9 succeed.
Link-Up Issue In Forced 100BASE-TX Mode
Issue: While in the forced 100BASE-TX mode with the automatic crossover detection
feature (HP Auto-MDIX) enabled, it can take up to several minutes for the link-up
process between the VSC8601 device and a link partner that also has its automatic
crossover detection feature enabled. The problem has not been observed in any other
operation modes.
Implications: While working against some link partners, such as those by Marvell, it can
take up to several minutes for the link-up process to complete.
Workaround: When forcing 100BASE-TX mode, use the following script to alter the
internal method that the VSC8601 uses to perform crossover detection. For more
information, see PHY API Software and Programmers Guide, which is available on the
Vitesse Web site at www.vitesse.com.
PhyWrite (PortNo, reg_num(dec), 16_bit_unsigned_data(hex))
PhyWriteMsk (PortNo, reg_num(dec), 16_bit_unsigned_data(hex), mask(hex))
Design Considerations
VSC8601 Datasheet
Page 96