VSC8601XKN Vitesse Semiconductor Corp, VSC8601XKN Datasheet - Page 87

• Manufacturer Part Number: VSC8601XKN
• Description: IC PHY 10/100/1000 64-EP-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8601XKN

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP Exposed Pad, 64-eLQFP, 64-HLQFP
• Case: TQFP
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1028

Table 80.
6.2.3
Table 81.
Revision 4.1
September 2009
RGMII MAC Interface Pins (continued)
Serial Management Interface (SMI)
The following table lists the device pins associated with the device serial management
interface (SMI). Note that the pins in this table are referenced to VDDIO
be set to a 2.5 V, or 3.3 V power supply.
SMI Pins
Pin
43
Pin
13
14
12
9
Name
OSCEN/CLKOUT
Name
MDC
MDIO
MDINT
EEDAT
OS/OD
Type
I
Type
I
PU
PD
I/O
I
PU
/O
/O
Description
OSCEN. This pin is sampled on the rising edge of
Description
Management data input/output pin. Serial data is
device configures this pin, along with others from
other devices, as active-low (open drain) or
active-high (open source) based on the polarity of
an external 10 kΩ resistor connection. These pins
can be tied together in a wired-OR configuration
with only a single pull-up or pull-down resistor.
(Optional) EEPROM serial I/O data. Used to
NRESET. If HIGH (or left floating), then the
on-chip oscillator circuit is enabled. If LOW, the
oscillator circuit is disabled and the device must be
supplied with a 25 MHz or 125 MHz reference
clock to the REFCLK pin.
CLKOUT. After NRESET is deasserted and OSCEN
state is established, this pin becomes the clock
output. The clock output can be enabled or
disabled through a CMODE pin setting. Also, it can
generate a reference clock frequency of 125 MHz.
This pin is not active when NRESET is asserted.
When disabled, the pin is held low.
Management data clock. A 0 MHz to 12.5 MHz
reference input is used to clock serial MDIO data
into and out of the PHY.
written or read from this pin bidirectionally
between the PHY and station manager,
synchronously on the positive edge of MDC. One
external pull-up resistor is required at the station
manager, and its value depends on the MDC clock
frequency and the total sum of the capacitive loads
from the MDIO pins.
Management interrupt signal. After reset, the
configure PHYs in a system without a station
manager. Connect to the SDA pin of the ATMEL
“AT24CXXX” serial EEPROM device family.
The VSC8601 determines that an external EEPROM
is present by monitoring the EEDAT pin at
power-up or when NRESET is de-asserted. If
EEDAT has a 4.7 kΩ external pull-up resistor, the
VSC8601 assumes an EEPROM is present. The
EEDAT pin can be left floating or grounded to
indicate no EEPROM.
VSC8601 Datasheet
Pin Descriptions
MICRO
and can
Page 87