VSC8601XKN Vitesse Semiconductor Corp, VSC8601XKN Datasheet - Page 34

• Manufacturer Part Number: VSC8601XKN
• Description: IC PHY 10/100/1000 64-EP-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8601XKN

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP Exposed Pad, 64-eLQFP, 64-HLQFP
• Case: TQFP
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1028

Figure 15.
3.13.8
Revision 4.1
September 2009
includes all IEEE-required signals (TMS, TCK, TDI, and TDO), in addition to the optional
asynchronous reset signal NTRST.
The following illustration shows the TAP and boundary-scan architecture.
Test Access Port and Boundary-Scan Architecture
After a TAP reset, the Device Identification register is serially connected between TDI
and TDO by default. The TAP Instruction register is loaded either from a shift register
(when a new instruction is shifted in) or, if there is no new instruction in the shift
register, a default value of 0110 (IDCODE) is loaded. Using this method, there is always
a valid code in the instruction register, and the problem of toggling instruction bits
during a shift is avoided. Unused codes are mapped to the BYPASS instruction.
JTAG Instruction Codes
The VSC8601 device supports the following instruction codes:
EXTEST Allows testing of off-chip circuitry and board-level interconnections by
sampling input pins and loading data onto output pins. Outputs are driven by the
contents of the boundary-scan cells, which have to be updated with valid values (with
the PRELOAD instruction) prior to the EXTEST instruction.
TDI
TMS
NTRST
TCK
Test Access Port
Controller
Device Identification
Instruction Register,
Instruction Decode,
Bypass Register
Boundary-Scan
Register
Register
Control
Control
Select
tdoenable
Control
Functional Descriptions
Mux,
DFF
VSC8601 Datasheet
Page 34
TDO