PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 103

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 9-7:
© 2006 Microchip Technology Inc.
RC0/T1OSO/
T1CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK1/SCL1
RC4/SDI1/SDA1
RC5/SDO1
RC6/TX/CK
RC7/RX/DT
Legend:
Note 1:
2:
Pin
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I
Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3.
Enhanced PWM output is available only on PIC18F44J10/45J10 devices.
2
C/SMB = I
PORTC I/O SUMMARY
Function
CCP2
T1OSO
T1CKI
T1OSI
P1A
CCP1
SCK1
SDA1
SDO1
SCL1
SDI1
RC0
RC1
RC2
RC3
RC5
RC6
RC7
RC4
CK
TX
RX
DT
2
C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
(2)
(1)
Setting
TRIS
0
1
x
1
0
1
x
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
2
C/SMB I
C/SMB I
Type
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
PORTC<0> data input.
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
Timer1 counter input.
PORTC<1> data input.
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2 compare and PWM output; takes priority over port data.
CCP2 capture input.
LATC<2> data output.
PORTC<2> data input.
ECCP1/CCP1 compare or PWM output; takes priority over port data.
ECCP1/CCP1 capture input.
ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
PORTC<3> data input.
SPI clock input (MSSP1 module).
I
PORTC<4> data input.
SPI data input (MSSP1 module).
I
PORTC<5> data input.
PORTC<6> data input.
Asynchronous serial transmit data output (EUSART module);
takes priority over port data. User must configure as output.
over port data.
Synchronous serial clock input (EUSART module).
PORTC<7> data input.
Asynchronous serial receive data input (EUSART module).
port data.
configure as an input.
LATC<0> data output.
LATC<1> data output.
LATC<3> data output.
SPI™ clock output (MSSP1 module); takes priority over port data.
LATC<4> data output.
LATC<5> data output.
SPI data output (MSSP1 module); takes priority over port data.
LATC<6> data output.
Synchronous serial clock output (EUSART module); takes priority
LATC<7> data output.
Synchronous serial data output (EUSART module); takes priority over
Synchronous serial data input (EUSART module). User must
2
2
2
2
C™ clock output (MSSP1 module); takes priority over port data.
C clock input (MSSP1 module); input type depends on module setting.
C data output (MSSP1 module); takes priority over port data.
C data input (MSSP1 module); input type depends on module setting.
PIC18F45J10 FAMILY
Description
DS39682B-page 101