PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 108

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
9.6
Depending on the particular PIC18F45J10 family
device selected, PORTE is implemented in two
different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/
AN7) are individually configurable as inputs or outputs.
These pins have Schmitt Trigger input buffers. When
selected as analog inputs, these pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
DS39682B-page 106
Note:
Note:
PORTE, TRISE and LATE
Registers
PORTE is only available in 40/44-pin
devices.
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
Preliminary
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 9-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
EXAMPLE 9-6:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTE
LATE
0Ah
ADCON1
03h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
INITIALIZING PORTE
© 2006 Microchip Technology Inc.