PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 185

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.4.17.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user deasserts SDAx and the pin is allowed
to float high, the BRG is loaded with SSPxADD<6:0>
and counts down to ‘0’. The SCLx pin is then
deasserted and when sampled high, the SDAx pin is
sampled.
FIGURE 15-29:
FIGURE 15-30:
© 2006 Microchip Technology Inc.
A low level is sampled on SDAx when SCLx
goes from low level to high level.
SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
SDAx
SCLx
BCLxIF
RSEN
S
SSPxIF
SDAx
SCLx
RSEN
BCLxIF
S
SSPxIF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
Preliminary
T
BRG
PIC18F45J10 FAMILY
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 15-29). If SDAx is sampled high, the BRG is
reloaded and begins counting. If SDAx goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDAx at
exactly the same time.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition (see Figure 15-30).
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
T
BRG
Cleared in software
Interrupt cleared
in software
‘0’
‘0’
DS39682B-page 183
‘0’