PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 220

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
17.8
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
acquisition period with minimal software overhead
TABLE 17-2:
DS39682B-page 218
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(1)
(1)
(1)
Use of the CCP2 Trigger
These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
A/D Result Register High Byte
A/D Result Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
PSPIF
PSPIE
PSPIP
OSCFIE
OSCFIP
OSCFIF
ADCAL
ADFM
Bit 7
RB7
IBF
—
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
(1)
(1)
bits
CMIF
CMIE
CMIP
ADIE
ADIP
ADIF
Bit 6
OBF
RB6
—
—
—
—
—
—
—
(CCP2CON<3:0>)
TRISA5
VCFG1
ACQT2
CHS3
RCIF
RCIE
RCIP
IBOV
Bit 5
RA5
RB5
—
—
—
—
—
PSPMODE
VCFG0
ACQT1
INT0IE
Preliminary
CHS2
TXIF
TXIE
TXIP
be
Bit 4
RB4
—
—
—
—
—
—
—
SSP1IE
SSP1IP
TRISA3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
PCFG3
ACQT0
CHS1
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 counter.
RBIE
Bit 3
RA3
RB3
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISA2
TRISE2
PCFG2
ADCS2
CHS0
Bit 2
RA2
RB2
RE2
—
—
—
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TRISA1
TRISE1
PCFG1
ADCS1
INT0IF
Bit 1
© 2006 Microchip Technology Inc.
RA1
RB1
RE1
—
—
—
ACQ
time selected before
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
CCP2IF
TRISA0
TRISE0
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
RB0
RE0
on page
Values
Reset
43
45
45
45
45
45
45
44
44
44
44
44
46
46
46
46
46
46
46
46