PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 265

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
CNT
If CNT
PC
If CNT
PC
Q1
Q1
No
Q1
No
No
=
=
=
=
≠
=
register ‘f’
operation
operation
operation
Increment f, Skip if 0
INCFSZ
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) + 1 → dest,
skip if result = 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
Q2
Q2
Q2
No
No
No
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
by a 2-word instruction.
f {,d {,a}}
INCFSZ
:
:
11da
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
ffff
CNT, 1, 0
destination
operation
operation
operation
Write to
Q4
Q4
No
Q4
No
No
ffff
Preliminary
PIC18F45J10 FAMILY
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
REG
If REG
PC
If REG
PC
No
No
Q1
Q1
No
Q1
=
=
≠
=
=
=
operation
operation
register ‘f’
operation
Increment f, Skip if not 0
INFSNZ
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) + 1 → dest,
skip if result ≠ 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
Q2
Q2
Q2
No
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
3 cycles if skip and followed
by a 2-word instruction.
f {,d {,a}}
INFSNZ
10da
operation
operation
operation
Process
Data
No
No
Q3
Q3
No
Q3
DS39682B-page 263
REG, 1, 0
ffff
destination
operation
operation
operation
Write to
No
No
Q4
Q4
No
Q4
ffff