PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 130

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
13.4
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP2 pin an output.
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 13.4.4
“Setup for PWM Operation”.
FIGURE 13-3:
A PWM output (Figure 13-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
FIGURE 13-4:
DS39682B-page 128
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
Note:
CCPRxH (Slave)
Comparator
Duty Cycle Registers
CCPRxL
TMR2
TMR2 = PR2
PR2
Comparator
PWM Mode
internal Q clock, or 2 bits of the prescaler, to create the
10-bit time base.
Duty Cycle
Clearing the CCP2CON register will force
the RB3 or RC1 output latch (depending on
device configuration) to the default low
level. This is not the PORTB or PORTC I/O
data latch.
Period
(Note 1)
Clear Timer,
CCP1 pin and
latch D.C.
TMR2 = Duty Cycle
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 = PR2
CCPxCON<5:4>
R
S
Q
Corresponding
TRIS bit
CCPx Output
Preliminary
13.4.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 13-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPRxL into
13.4.2
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 13-2:
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPRxH is a read-only register.
cycle = 0%, the CCPx pin will not be set)
CCPRxH
Note:
PWM Duty Cycle = (CCPR
PWM Period = [(PR2) + 1] • 4 • T
PWM PERIOD
The Timer2 postscalers (see Section 12.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
T
(TMR2 Prescale Value)
OSC
© 2006 Microchip Technology Inc.
• (TMR2 Prescale Value)
X
L:CCP
X
CON<5:4>) •
OSC
•