PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 176

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
15.4.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPxADD<6:0> and
starts its count. If SCLx and SDAx are both sampled
high when the Baud Rate Generator times out (T
the SDAx pin is driven low. The action of the SDAx
being driven low while SCLx is high is the Start condi-
tion and causes the S bit (SSPxSTAT<3>) to be set.
Following this, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and resumes its
count. When the Baud Rate Generator times out
(T
cally cleared by hardware. The Baud Rate Generator is
suspended, leaving the SDAx line held low and the
Start condition is complete.
FIGURE 15-19:
DS39682B-page 174
BRG
), the SEN bit (SSPxCON2<0>) will be automati-
I
CONDITION TIMING
2
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
SDAx
SCLx
SDAx = 1,
SCLx = 1
T
BRG
BRG
Preliminary
),
Set S bit (SSPxSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
15.4.8.1
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
and sets SSPxIF bit
Note:
Note:
Write to SSPxBUF occurs here
T
BRG
1st bit
If at the beginning of the Start condition,
the SDAx and SCLx pins are already sam-
pled low, or if during the Start condition, the
SCLx line is sampled low before the SDAx
line is driven low, a bus collision occurs.
The Bus Collision Interrupt Flag, BCLxIF,
is set, the Start condition is aborted and
the I
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
WCOL Status Flag
T
BRG
2
C module is reset into its Idle state.
© 2006 Microchip Technology Inc.
2nd bit