ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 18

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
18
Table 4.
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Table 4
Intel
PBGA
Pin#
C4
C5
D6
C8
A3
B3
A4
B4
B8
A8
A7
A5
B5
B6
B2
®
LXT971A Transceiver MII Data Interface Signal Descriptions (Sheet 1 of 2)
lists signal descriptions of the LXT971A Transceiver MII data interface pins.
LQFP
Pin#
60
59
58
57
56
55
45
46
47
48
49
53
54
52
62
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_ER
TX_ER
RX_CLK
COL
Symbol
Type
O
O
O
O
O
O
I
I
I
Transmit Data.
TXD is a group of parallel data signals that are driven by the MAC.
TXD[3:0] transition synchronously with respect to TX_CLK.
TXD[0] is the least-significant bit.
Transmit Enable.
The MAC asserts this signal when it drives valid data on TXD.
This signal must be synchronized to TX_CLK.
Transmit Clock.
TX_CLK is sourced by the PHY in both 10 and 100 Mbps
operations.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
Receive Data.
RXD is a group of parallel signals that transition synchronously with
respect to RX_CLK.
RXD[0] is the least-significant bit.
Receive Data Valid.
The LXT971A Transceiver asserts this signal when it drives valid
data on RXD.
This output is synchronous to RX_CLK.
Receive Error.
Signals a receive error condition has occurred.
This output is synchronous to RX_CLK.
Transmit Error.
Signals a transmit error condition.
This signal must be synchronized to TX_CLK.
Receive Clock.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
For details, see
“Functional
Collision Detected.
The LXT971A Transceiver asserts this output when a collision is
detected.
This output remains High for the duration of the collision.
This signal is asynchronous and is inactive during full- duplex
operation.
Description”.
“Clock Requirements” on page 32
Signal Description
Document Number: 249414-003
Revision Date: June 18, 2004
in
Chapter 5.0,
Datasheet