ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 36

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
5.4.2.3
5.4.3
36
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Note:
Sleep Mode
The LXT971A Transceiver supports a power-saving sleep mode. Sleep mode is enabled when
SLEEP is asserted via pin 32(LQFP)/H7(PBGA). The value of pin 32/H7 can be overridden by
Register bit 16.6 in managed mode as listed in
Hex 10” on page
and no energy is detected on the twisted-pair input for 1 to 3 seconds. (The time is controlled by
Register bits 16.4:3 in the Configuration Register, with a default of 3.04 seconds.)
During this mode, the LXT971A Transceiver still responds to management transactions (MDC/
MDIO). In this mode the power consumption is minimized, and the supply current is reduced
below the maximum value given in
activity on the twisted-pair inputs, it comes out of the sleep state and checks for link. If no link is
detected in from 1 to 3 seconds (the time is programmable) it reverts to the low power sleep state.
Sleep mode is not functional in fiber network applications.
Reset for Intel
The LXT971A Transceiver provides both hardware and software resets, each of which manage
differently the configuration control of auto-negotiation, speed, and duplex-mode selection.
For a software reset, Register bit 0.15 = 1. For register bit definitions used for software reset, see
Table 45, “Control Register - Address 0, Hex 0” on page
For pin settings used during a hardware reset, see
Settings”. During a hardware reset, configuration settings for auto-negotiation and speed are read
in from pins, and register information is unavailable for 1 ms after de-assertion of the reset.
•
•
During a software reset, bit settings in
Address 4, Hex 4” on page 92
pins. Instead, the bit settings revert to the values that were read in during the last hardware
reset. Therefore, any changes to pin values made since the last hardware reset are not detected
during a software reset.
During a software reset, registers are available for reading. To see when the LXT971A
Transceiver has completed reset, the reset bit can be polled (that is, Register bit 0.15 = 0).
97. The LXT971A Transceiver enters into sleep mode when SLEEP is enabled
®
LXT971A Transceiver
are not re-read from the LXT971A Transceiver configuration
Table 21 on page
Table 49, “Auto-Negotiation Advertisement Register -
Table 55, “Configuration Register - Address 16,
Section 5.4.4, “Hardware Configuration
70. If the LXT971A Transceiver detects
88.
Document Number: 249414-003
Revision Date: June 18, 2004
Datasheet