ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 74

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ELLXT971ABE.A4

Manufacturer Part Number
ELLXT971ABE.A4
Description
IC TRANS 3.3V ETHERNET 64-BGA
Manufacturer
Intel
Type
PHY Transceiverr
Datasheet

Specifications of ELLXT971ABE.A4

Number Of Drivers/receivers
1/1
Protocol
IEEE 802
Voltage - Supply
3.14 V ~ 3.45 V
Mounting Type
Surface Mount
Package / Case
64-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
870479

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74
Table 27. 100BASE-TX Transceiver Characteristics
Table 28. 100BASE-FX Transceiver Characteristics
Table 29. 10BASE-T Transceiver Characteristics (Sheet 1 of 2)
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Table 27
Table 28
Table 29
Peak differential output voltage
Signal amplitude symmetry
Signal rise/fall time
Rise/fall time symmetry
Duty cycle distortion
Overshoot/Undershoot
Jitter (measured differentially)
Peak differential output voltage
(single ended)
Signal rise/fall time
Jitter (measured differentially)
Peak differential input voltage
Common mode input range
Peak differential output
voltage
Transition timing jitter added
by the MAU and PLS
sections
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
2. Measured at the line side of the transformer, line replaced by 100 Ω (+/-1%) resistor.
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
testing.
testing.
Parameter
lists the 100BASE-TX characteristics.
lists the 100BASE-FX characteristics.
lists the 10BASE-T characteristics.
Parameter
Parameter
Symbol
V
Symbol
V
OP
Symbol
V
T
V
CMIR
T
D
OP
RF
Vss
V
T
IP
V
RFS
OS
RF
CD
P
Min
2.2
0
0.55
Min
0.6
0.95
Min
Transmitter
3.0
Transmitter
35
98
Receiver
Typ
2.5
Typ
Typ
2
50
1
1
V
Max
1.05
Max
102
2.8
5.0
0.5
1.4
CC
65
11
5
Max
1.5
1.9
1.5
1.3
- 0.7
Units
Units
ns
ns
ns
%
%
%
V
ns
V
Units
ns
ns
Document Number: 249414-003
V
V
V
Revision Date: June 18, 2004
Offset from 16 ns pulse
width at 50% of pulse
peak
With transformer, line
replaced by 100 Ω
resistor
After line model
specified by IEEE
802.3 for 10BASE-T
MAU
Test Conditions
Test Conditions
Test Conditions
10 <–> 90%
2.0 pF load
Note 2
Note 2
Note 2
Note 2
Datasheet

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