ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 22

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
22
Table 9.
Table 10. Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Note:
Table 9
Intel
Table 10
If a JTAG port is not used, these pins do not need to be terminated.
C3, G7,
D4, E3,
E4, F3,
F4, C6,
G3, G4
E5, D5
B7, C7
PBGA
PBGA
Pin#
Pin#
G8
G5
G6
A6
H6
F5
F6
D7
®
®
LXT971A Transceiver Power, Ground, No-Connect Signal Descriptions
LXT971A Transceiver JTAG Test Signal Descriptions
lists signal descriptions of the LXT971A Transceiver power, ground, and no-connect pins.
lists signal descriptions of LXT971A Transceiver Joint Test Action Group (JTAG) pins.
LQFP
18, 25,
34, 35,
41, 50,
LQFP
21, 22
Pin#
7, 11,
9, 10,
8, 40
Pin#
27
28
29
30
31
51
61
44
TDI
TDO
TMS
TCK
TRST_L
VCCD
GND
VCCIO
VCCA
NC
Symbol
Symbol
Type
Type
O
–
–
–
–
I
I
I
I
-
Digital Power.
Requires a 3.3 V power supply.
Ground.
MII Power.
Requires either a 3.3 V or a 2.5 V supply. Must be supplied
from the same source used to power the MAC on the other
side of the MII.
Analog Power.
Requires a 3.3 V power supply.
No Connection.
These pins are not used and should not be terminated.
Test Data Input.
Test data sampled with respect to the rising edge of TCK.
Test Data Output.
Test data driven with respect to the falling edge of TCK.
Test Mode Select.
Test Clock.
Clock input for boundary scan.
Test Reset.
This active-low test reset input is sourced by ATE.
Signal Description
Signal Description
Document Number: 249414-003
Revision Date: June 18, 2004
Datasheet