ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 55

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

5.8
5.8.1
5.8.2
5.8.3
Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Note: The LXT971A Transceiver does not support fiber connections at 10 Mbps.
10 Mbps Operation
The LXT971A Transceiver operates as a standard 10BASE-T transceiver and LXT971A supports
standard 10 Mbps functions. During 10BASE-T operation, the LXT971A Transceiver transmits
and receives Manchester-encoded data across the network link. When the MAC is not actively
transmitting data, the LXT971A Transceiver drives link pulses onto the line.
In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded
signals received from the network are decoded by the LXT971A Transceiver and sent across the
MII to the MAC.
10BASE-T Preamble Handling
The LXT971A Transceiver offers two options for preamble handling, selected by Register bit 16.5.
10BASE-T Carrier Sense
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and CRS de-assertion
is based on reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion
to be synchronized with RX_DV de-assertion. For details, see
Address 16, Hex 10” on page
10BASE-T Dribble Bits
The LXT971A Transceiver handles dribble bits in all modes. If one to four dribble bits are
received, the nibble is passed across the MII, padded with ones if necessary. If five to seven
dribble bits are received, the second nibble is not sent to the MII bus.
•
•
In 10BASE-T mode when Register bit 16.5 = 0, the LXT971A Transceiver strips the entire
preamble off of received packets. CRS is asserted coincident with the start of the preamble.
RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first
two nibbles driven by the LXT971A Transceiver are the SFD “5D” hex followed by the body
of the packet.
In 10BASE-T mode when Register bit 16.5 = 1, the LXT971A Transceiver passes the
preamble through the MII and asserts RX_DV and CRS simultaneously. (In 10BASE-T
loopback, the LXT971A Transceiver loops back whatever the MAC transmits to it, including
the preamble.)
97.
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Table 55, “Configuration Register -
55