ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 68

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
68
Figure 26. Typical Interface - Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
The following occurs in 5 V fiber transceiver applications as shown in
Figure 26
fiber transceiver.
•
•
•
•
The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels.
The transmit pair should contain a balance offset in the bias resistors to prevent PHY-to-fiber
transceiver crosstalk amplification in power-down, loopback, and reset states. (See the fiber
interface application note.)
The receive pair should be AC-coupled with an emitter current path for the fiber transceiver
and re-biased to 3.3 V LVPECL input levels.
The signal detect pin on a 5 V fiber transceiver interface should use the logic translator
circuitry as shown in
1. Refer to the transceiver manufacturers’ recommendations for termination circuitry.
2. See
Transceiver
LXT971A
shows a typical example of an interface between the LXT971A Transceiver and a 5 V
Intel®
Figure 26
SD/TP_L
TPFON
TPFOP
TPFIN
TPFIP
for recommended logic translator interface circuitry.
+3.3 V
Figure
16 Ω
50 Ω
0.01 μF -
®
0.1 μF
LXT971A Transceiver to 5 V Fiber Transceiver
+3.3 V
+3.3 V
26.
2
50 Ω
0.01μF -
0.1μF
102 Ω
154 Ω
ON Semiconductor*
PECL-to-LVPECL
Logic Translator
0.01 μF
0.01 μF
MC100LVEL92
102 Ω
154 Ω
0.01 μF
0.01 μF
1.15 kΩ
3.1 kΩ
270 Ω
1.1 kΩ
+5 V
270 Ω
3.1 kΩ
TD +
TD -
RD +
Fiber Txcvr
SD
RD -
0.01 μF -
0.1 μF
5 V
1
Figure
Document Number: 249414-003
B3403-01
Revision Date: June 18, 2004
26:
Datasheet