Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 150
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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Table 73. LIN-UART Status 0 Register – Standard UART Mode (UxSTAT0)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
7
6
5
4
3
2
1
Description
RDA – Receive Data Available
This bit indicates that the LIN-UART receive data register has received data. Reading the LIN-
UART receive data register clears this bit.
0 = The LIN-UART receive data register is empty.
1 = There is a byte in the LIN-UART receive data register.
PE – Parity Error
This bit indicates that a parity error has occurred. Reading the receive data register clears this
bit.
0 = No parity error occurred.
1 = A parity error occurred.
OE – Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the receive data register has not been read. Reading the receive data register
clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
FE – Framing Error
This bit indicates that a framing error (no Stop bit following data reception) is detected. Read-
ing the receive data register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
BRKD – Break Detect
This bit indicates that a break has occurred. If the data bits, parity/multiprocessor bit and Stop
bit(s) are all zeroes then this bit is set to 1. Reading the receive data register clears this bit.
0 = No break occurred.
1 = A break occurred.
TDRE – Transmitter Data Register Empty
This bit indicates that the transmit data register is empty and ready for additional data. Writing
to the transmit data register resets this bit.
0 = Do not write to the transmit data register.
1 = The transmit data register is ready to receive an additional byte to be transmitted.
TXE – Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
RDA
R
7
0
PE
R
6
0
OE
R
5
0
P R E L I M I N A R Y
FF_E201H, FF_E211H
FE
R
4
0
BRKD
Z16FMC Series Motor Control MCUs
R
3
0
TDRE
R
2
1
Product Specification
TXE
R
1
1
LIN-UART
CTS
R
X
0
128
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