Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 269
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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Table 142. Flash Sector Protect Register (FSECT)
Table 143. Flash Page Select Register (FPAGE)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
R/W1 = Register is accessible for Read operations. Register is written to 1 only (via user code).
Bits
7:0
Note: *User code write bits from 0 to 1 only.
Bits
Field
RESET
R/W
ADDR
Bits
15:9
Flash Sector Protect Register
Flash Page Select Register
Description
SECTn – Sector Protect
0 = Sector n is programmed or erased from user code.
1 = Sector n is protected and cannot be programmed or erased from user code.
Description
Reserved
These bits are reserved and are 0.
15
SECT7
R/W1
7
0
The Flash Sector Protect register (see Table 142) protects Flash memory sectors from
being programmed or erased from user code. User code can only write bits in this register
to 1 (bits cannot be cleared to 0 by user code).
The Flash Page Select (FPAGE) register (see Table 143) selects one of the 64 available
Flash memory pages to be erased or programmed. Each Flash Page contains 2048 words
of Flash memory. During a Page Erase operation, all Flash memory locations within the
page will be erased to
14
13
SECT6
R/W1
Reserved
6
0
00H
12
R
11
SECT5
R/W1
FFFFH
5
0
10
P R E L I M I N A R Y
.
FF_E064-FF_E065H
9
SECT4
R/W1
4
0
FF_E062H
8
7
SECT3
R/W1
Z16FMC Series Motor Control MCUs
3
0
6
PAGE
R/W
00H
5
SECT2
R/W1
2
0
4
Product Specification
3
SECT1
R/W1
1
0
2
Flash Memory
Reserved
0H
R
1
SECT0
R/W1
0
0
0
247
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