Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 173
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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- Download datasheet (21Mb)
PS028702-1210
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
Transfer Format with Phase Equals Zero
Figure 26 displays the timing diagram for an SPI type transfer in which PHASE =
SPI transfers the clock only toggles during the character transfer. The two SCK wave-
forms show polarity with CLKPOL =
as either a Master or Slave timing diagram as the SCK MISO and MOSI pins are directly
connected between the master and the slave.
Transfer Format with Phase Equals One
Figure 27 displays the timing diagram for an SPI type transfer in which PHASE
SPI transfers the clock only toggles during the character transfer. Two waveforms are
depicted for SCK, one for CLKPOL =
MOSI
MISO
SCK
SCK
SS
Bit7
Bit7
Figure 26. ESPI Timing When
Bit6
Bit6
P R E L I M I N A R Y
Bit5
Bit5
0
0
Bit4
Bit4
and with CLKPOL =
and another for CLKPOL =
Bit3
Bit3
Z16FMC Series Motor Control MCUs
PHASE
Enhanced Serial Peripheral Interface
Bit2
Bit2
= 0
1
. The diagram is interpreted
Bit1
Bit1
Product Specification
1
.
Bit0
Bit0
= 1
0
. For
. For
151
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