Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 222
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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Table 105. I
PS028702-1210
Bits
7
6
5
4
3
2
1
0
Bits
Field
RESET
R/W
ADDR
Description
ACKV – ACK valid
This bit is set if sending data (Master or Slave) and the ACK bit in this register is valid for the
byte just transmitted. This bit is monitored if it is appropriate for software to verify the ACK value
before writing the next byte to be sent. To operate in this mode, the data register must not be
written when TDRE asserts; instead, software waits for ACKV to assert. This bit clears when
transmission of the next byte begins or the transaction is ended by a STOP or RESTART con-
dition.
ACK – Acknowledge
This bit indicates the status of the Acknowledge for the final byte transmitted or received. This
bit is set for an Acknowledge and cleared for a Not Acknowledge condition.
AS – Address state
This bit is active High while the address is being transferred on the I
DS – Data state
This bit is active High while the data is being transferred on the I
10B
This bit indicates whether a 10 or 7-bit address is being transmitted when operating as a Mas-
ter. After the START bit is set, if the five most-significant bits of the address are 11110B, this bit
is set. When set, it is reset after the address has been sent.
RSTR – RESTART
This bit is updated each time a STOP or RESTART interrupt occurs (SPRS bit set in I2CISTAT
register).
0 = Stop condition
1 = Restart condition
SCLOUT – Serial Clock Output
Current value of Serial Clock being output onto the bus. The actual values of the SCL and SDA
signals on the I
BUSY – I
0 = No activity on the I
1 = A transaction is underway on the I
2
C State Register (I2CSTATE) – Description when DIAG = 1
R
7
0
2
C bus busy
2
C bus is observed via the GPIO Input register.
R
6
I2CSTATE_H
0
2
C Bus.
R
5
0
P R E L I M I N A R Y
2
C bus.
R
4
0
FF_E245H
Z16FMC Series Motor Control MCUs
R
3
0
2
R
2
I2CSTATE_L
0
C bus.
I2C Master/Slave Controller
2
C bus.
Product Specification
R
1
0
R
0
0
200
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