Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 283
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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- Download datasheet (21Mb)
PS028702-1210
Initialization
Initialization during Reset
If the standard serial port of a PC is used, transmit flow control is enabled on the Z16FMC
Series device. The PC sends the start bit when receiving data by transmitting the character
FFH. Because character FFH is also received from a non-responsive device, space parity
(parity bit always zero) must be enabled and used as an acknowledge bit.
The OCD ignores any data received until it receives the read revision command
the read revision command is received, the remaining debug commands are issued. The
packet CRC is not sent for the first read revision command issued during initialization.
The OCD is initialized during reset by asserting the reset pin, sending the auto-baud char-
acter and then issuing the read revision command. When the OCD is initialized during
reset, the
Receiving
Device
Transmitting
Device
Single Wire
Bus
DBGHALT
ST = Start Bit
SP = Stop Bit
D0-D7 = Data Bits
Figure 56. Start Bit Flow Control
bit in the OCDCTL register is automatically set.
ST
ST
D0
D0
P R E L I M I N A R Y
D1
D1
D2
D2
D3
D3
D4
D4
Z16FMC Series Motor Control MCUs
D5
D5
D6
D6
D7
D7
Product Specification
SP
SP
On-Chip Debugger
00H
. After
261
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