Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 171
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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Operation
PS028702-1210
•
•
•
During transfer, data is sent and received simultaneously by both master and slave
devices. Separate signals are required to transmit data, receive data and the serial clock.
When a transfer occurs, a multibit (typically 8-bit) character is shifted out one data pin and
a multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift regis-
ter in the master and an 8-bit shift register in the slave is connected as a circular buffer.
The ESPI shift register is buffered to support back-to-back character transfers in high per-
formance applications.
A transaction is initiated when the transmit data register is written in the master device.
The value from the data register is transferred into the shift register and the transaction
begins. After the transmit data is loaded into the shift register, the Transmit Data Register
Empty (TDRE) status bit asserts, indicating that transmit data register is written with the
next value. At the end of each character transfer, the shift register value (receive data) is
loaded into the receive data register. At that point the Receive Data Register Full (RDRF)
status bit asserts. When software or DMA reads the receive data from the receive data reg-
ister, the RDRF signal deasserts.
The master sources the SCK and SS signal during the transfer.
Internal data movement (either by software or DMA) to/from the ESPI block is controlled
by the transmit data register empty (TDRE) and receive data register full (RDRF) signals.
These signals are read only bits in the ESPI status register. When either the TDRE or
RDRF bits assert, an interrupt is sent to the interrupt controller if the data interrupt request
–
–
Mode register:
–
–
–
Status register:
–
–
State register:
–
–
STR bit on the SPI module replaced with ESPIEN1; SPIEN replaced by
ESPIEN0; these enhancements allow unidirectional transfers, which minimize
software or DMA overhead
BIRQ replaced with BRGCTL
Added SSMD field which adds support for loop back and I2S modes
Moved SSV bit to the transmit data command register, as described above
Added slave select polarity (SSPO) to support active High and Low slave select
on SS pin
IRQ split into TDRE and RDRF (separate transmit and receive interrupts)
Replace overrun error with separate transmit under-run and receive overrun
Replaced SCKEN bit with SCKI
Replaced TCKEN with SDI
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Enhanced Serial Peripheral Interface
Product Specification
149
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