Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 210
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
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Quantity:
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PS028702-1210
2. The Master initiates a transfer by sending the first address byte. The I
3. The Master sends the second address byte. The Slave mode I
4. Software responds to the interrupt by reading the I2CISTAT Register, which clears the
5. The Master detects the Acknowledge and sends the first byte of data.
6. The I
7. Software responds by reading the I2CISTAT Register, finding the
8. The Master and Slave loops on steps 5–7 until the Master detects a Not Acknowledge
9. The Master sends the STOP or RESTART signal on the bus. Either of these signals
–
–
–
–
–
recognizes the start of a 10-bit address with a match to
bit = 0 (write from Master to Slave). The I
it is available to accept the transaction.
address match between the second address byte and
I2CISTAT Register is set = 1, causing an interrupt. The
write to the Slave. The I
accept the data.
SAM
data is received. If software is only able to accept a single byte it sets the
I2CCTL Register.
Acknowledge, depending on the state of the
controller generates the receive data interrupt by setting the
Register.
then reading the I2CDATA Register, which clears the
only one more data byte, it sets the
instruction or runs out of data to send.
cause the I
Register). When the Slave receive data from the Master, software takes no action in
response to the Stop interrupt other than reading the I2CISTAT Register, clearing the
STOP bit.
Initialize the MODE field in the I2CMODE Register for either SLAVE-ONLY
mode or MASTER/SLAVE mode with 10-bit addressing
Optionally set the
Initialize the
I2CMODE Register
Set
Program the Baud Rate High and Low Byte registers for the I
bit. When
2
C controller receives the first byte and responds with Acknowledge or Not
IEN
2
C Controller to assert the Stop interrupt (STOP bit = 1 in the I2CISTAT
= 1 in the I2CCTL Register. Set
RD
SLA
= 0, no immediate action is taken by software until the first byte of
[7:0] bits in the I2CSLVAD Register and the
GCE
P R E L I M I N A R Y
2
C Controller Acknowledges, indicating it is available to
bit
NAK
bit in the I2CCTL Register.
2
C Controller acknowledges, indicating that
Z16FMC Series Motor Control MCUs
NAK
NAK
bit in the I2CCTL Register. The I
= 0 in the I
SLA
RDRF
SLA
RD
[7:0]. The
I2C Master/Slave Controller
bit is set = 0, indicating a
[9:8] and detects the R/W
RDRF
bit. If software accepts
Product Specification
2
2
C Control Register
C Controller detects an
2
bit in the I2CISTAT
RDRF
SLA
C baud rate
SAM
2
C Controller
[9:8] bits in the
bit in the
NAK
bit = 1 and
bit in the
2
C
188
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