Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 198
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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- Download datasheet (21Mb)
PS028702-1210
Start and Stop Conditions
I
when the I2CISTAT Register is read.
Stop/Restart Interrupts
A Stop/Restart event interrupt (
is in SLAVE mode and a Stop or Restart condition is received, indicating the end of the
transaction. The
was set due to a Stop or Restart condition. When a Restart occurs, a new transaction by the
same Master is expected to follow. This bit is cleared automatically when the I2CISTAT
Register is read. The Stop/Restart interrupt only occurs on a selected (address match)
slave.
Not Acknowledge Interrupts
Not Acknowledge interrupts (
Not Acknowledge is received or sent by the I
not set in the
interrupt clears by setting the START or STOP bit. When this interrupt occurs in Master
mode, the I
mode, the Not Acknowledge interrupt occurs when a Not Acknowledge is received in
response to the data sent. The
I2CISTAT Register.
General Purpose Timer Interrupt from Baud Rate Generator
If the I
the I2CCTL Register = 1, an interrupt is generated when the BRG counts down to 1. The
BRG reloads and continues counting, providing a periodic interrupt. None of the bits in
the I2CISTAT Register are set, allowing the BRG in the I
eral purpose timer when the I
The Master generates the Start and Stop conditions to start or end a transaction. To start a
transaction, the I
while SCL is High. To complete a transaction, the I
tion by creating a Low-to-High transition of the SDA signal while the SCL signal is High.
The START and STOP events occur when the START and STOP bits in the I
Register are written by software to begin or end a transaction. Any byte transfer currently
under way finishes, including the acknowledge phase before the START or STOP condi-
tion occurs.
2
C Controller switches to SLAVE mode when this occurs. This bit clears automatically
2
C Controller is disabled (
2
C Controller waits until it is cleared before performing any action. In SLAVE
I2C State Register
RSTR
2
C Controller generates a Start condition by pulling the SDA signal Low
bit in the
P R E L I M I N A R Y
2
NCKI
NCKI
C Controller is disabled.
SPRS
I2C State Register
(see page 199). In MASTER mode the Not Acknowledge
IEN
bit = 1 in I2CISTAT) occur in Master mode when a
bit clears in Slave mode when software reads the
bit = 1 in I2CISTAT) occurs when the I
bit in the I2CCTL Register = 0) and the
2
C Controller and the START or STOP bit is
Z16FMC Series Motor Control MCUs
(see page 199) indicates whether the bit
2
C Controller generates a STOP condi-
2
C Controller to be used as a gen-
I2C Master/Slave Controller
Product Specification
2
C Controller
2
BIRQ
C Control
bit in
176
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