Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 298
![Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
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Table 158. Debug Control Register (DBGCTL)
PS028702-1210
Bits
2
1
0
Bits
Field
RESET
R/W
ADDR
Bits
7
6
5:4
Debug Control Register
Description (Continued)
TXCOL – Transmit Collision
This bit is set when a Transmit Collision occurs. This bit is cleared by writing a one to this bit.
0 = No collision has been detected.
1 = Transmit Collision has been detected.
RXBUSY – Receiver Busy
This bit is set when the receiver is receiving the data. Multi-master systems uses this bit to
ensure the line is idle before sending the data.
0 = Receiver is idle.
1 = Receiver is receiving data.
TXBUSY – Transmitter Busy
This bit is set when the transmitter is sending the data. This bit is used to determine when to
turn off a transceiver for RS-485 applications.
0 = Transmitter is idle.
1 = Transmitter is sending the data.
Description
OCDLOCK – On-Chip Debug Lock
This bit locks the Debug Control Register so it cannot be written by the CPU. This bit is auto-
matically set if the DBGUART option bit is in its default erased state (one).
0 = Debug Control Register unlocked.
1 = Debug Control Register locked.
OCDEN – On-chip debug enable
This bit is set when the OCD is enabled. When this bit is set, received data is interpreted as
debug command. To use the DBG pin as a UART or GPIO pin, this bit must be cleared to zero
by software. This bit cannot be written by the CPU if OCDLOCK is set.
0 = OCD is disabled.
1 = OCD is enabled.
Reserved
These bits are reserved.
OCDLOCK
R/W
The Debug Debug Control Register (DBGCTL) sets the mode of the serial interface.
7
1
OCDEN
R/W
6
1
5
Reserved
P R E L I M I N A R Y
00
R
4
FF_E086
CRCEN
R/W
Z16FMC Series Motor Control MCUs
3
1
UARTEN
R/W
2
0
Product Specification
ABCHAR ABSRCH
R/W
On-Chip Debugger
1
0
R/W
0
1
276
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