ST92T163R4T1 STMicroelectronics, ST92T163R4T1 Datasheet - Page 136

• Manufacturer Part Number: ST92T163R4T1
• Description: Microcontrollers (MCU) OTP EPROM 20K USB/I2
• Manufacturer: STMicroelectronics

Specifications of ST92T163R4T1

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 20 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST92163 - USB PERIPHERAL (USB)
USB INTERFACE (Cont’d)
8.3.3.1 DMA transfer
DMA descriptors for each endpoint, located in the
ST9 register file, indicate where the related mem-
ory buffer is located in RAM, how large the allocat-
ed buffer is and how many bytes must be transmit-
ted. When a data transfer takes place, the USB-FS
buffering data loaded in an internal 8 byte long
FIFO buffer, and performing Burst-DMA transfers
as appropriate. Then, if needed, the proper hand-
shake answer is generated or expected, according
to the direction of the transfer. At the end of the
transaction, an interrupt is generated: using status
registers and different interrupt vectors, the micro-
controller can determine which endpoint was
served, which type of transaction took place, if er-
rors occurred (bit stuffing, format, CRC, protocol,
missing ACK, over/underrun, etc...).
8.3.3.2 Structure and usage of DMA buffers
Each endpoint has two DMA buffers (one for trans-
mission and the other for reception) whose size
may be up to 1023 bytes each. They can be
placed anywhere in memory (internally or exter-
nally).
For each endpoint, eight Register File locations
are used:
ADDRn_TH and ADDRn_TL: These registers
point to the starting address of the memory buffer
containing the data to be transmitted by endpoint n
at the next IN token addressed to it.
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COUNTn_TL and COUNTn_TH: These registers
contain the number of bytes to be transmitted by
endpoint n at the next IN token addressed to it.
ADDRn_RL and ADDRn_RH: These registers
point to the starting address of the memory buffer
which will contain the data received by endpoint n
at the next OUT/SETUP token addressed to it.
COUNTn_RL and COUNTn_RH: These registers
contain the allocated buffer size for endpoint n re-
ception, setting the maximum number of bytes the
related endpoint can receive with the next OUT/
SETUP transaction.
Other register locations related to unsupported
transfer directions or unused endpoints, are avail-
able to the user. Isochronous endpoints have a
special way of handling DMA buffers.
The relationship between register file locations
and memory buffer areas is depicted in Figure 70.
Each DMA buffer is used starting from the bottom,
either during reception or transmission.
The USB interface never changes the contents of
memory locations adjacent to the DMA memory
buffers; even if a packet bigger than the allocated
buffer length is received (buffer overrun condition)
the data will be copied in memory only up to the
last available location.