ST92T163R4T1 STMicroelectronics, ST92T163R4T1 Datasheet - Page 145

• Manufacturer Part Number: ST92T163R4T1
• Description: Microcontrollers (MCU) OTP EPROM 20K USB/I2
• Manufacturer: STMicroelectronics

Specifications of ST92T163R4T1

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 20 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

USB INTERFACE (Cont’d)
ENDPOINT n REGISTER B (EPnRB)
(RECEPTION)
R241-R255 (odd) - Read/Write
Register pages: 4 & 5
Reset value: 0000 0000 (00h)
These registers are used for controlling data re-
ception. They are also reset when a USB reset is
received from the USB bus or forced through bit
FRES in the USBCTLR register. Each endpoint
has its EPnRB register where n is the endpoint
identifier in the range 0 to 15.
Bit 7 = ST_OUT Status out .
This bit is set by software to indicate that a status
out transaction is expected: in this case all OUT
transactions containing more than zero data bytes
are answered STALL instead of ACK. This bit may
be used to improve the robustness of the applica-
tion to protocol errors during control transfers and
its usage is intended on control endpoints only.
When ST_OUT is reset, OUT transactions can
have any number of bytes, as needed.
Bit 6 = DTOG_RX: Data Toggle, for reception
transfers .
If the endpoint is non-isochronous, this bit contains
the expected value of the data toggle bit
(0=DATA0, 1=DATA1) for the next data packet to
be received. Hardware toggles this bit when the
ACK handshake is sent to the USB host, following
a data packet reception with a matching data PID
value. If the endpoint is defined as a control end-
point, hardware resets this bit on reception of a
SETUP PID addressed to this endpoint.
If the endpoint is isochronous, this bit is used to
support DMA buffer swapping since no data tog-
gling is used for this sort of endpoint and only
DATA0 packets are received. Hardware toggles
this bit just after the end of data packet reception,
ST_OU
7
T
DTOG_
RX
STAT_
RX1
STAT_
RX0
EnA3
EnA2
EnA1
EnA0
0
since no handshake is used for isochronous trans-
fers.
Note: this bit can be also written by software to in-
itialize it (mandatory when the endpoint is not a
control endpoint) or to force a specific data toggle/
DMA buffer usage.
Bit 5:4 = STAT_RX [1:0] Status bits, for reception
transfers .
These bits contain the information about the end-
point status, as listed below:
Table 28. Reception status encoding
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) related to a OUT or
SETUP (control only) transaction addressed to
this endpoint, so software has time to interpret the
received data before acknowledging a new trans-
action.
If the endpoint is defined as isochronous, its status
can be only “VALID” or “DISABLED” so no hard-
ware change of the endpoint status will take place
after a successful transaction.
Bit 3:0 = EnA[3:0] Endpoint n Address, bits 3-0.
Software must write in this field the 4-bit address
used to identify the transactions directed to this
endpoint. A value must be written before enabling
the corresponding endpoint.
STAT_TX
[1:0]
00
01
10
11
ST92163 - USB PERIPHERAL (USB)
DISABLED: all reception requests ad-
dressed to this endpoint are ignored.
STALL: the endpoint is stalled and all re-
ception requests result in a STALL hand-
shake.
NAK: the endpoint is naked and all recep-
tion requests result in a NAK handshake.
VALID: this endpoint is enabled for recep-
tion.
Meaning
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