M69000 Asiliant Technologies, M69000 Datasheet - Page 113

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9-20
CR10
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 10h
7-0
&+,36
7
Vertical Sync Start Bits 7-0
This register provides the 8 least significant bits of either a 10-bit or 12-bit value that specifies the
beginning of the vertical sync pulse relative to the beginning of the active display area of a screen.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, this value is
described in 10 bits with bits 7 and 2 of the Overflow Register (CR07) supplying the 2 most
significant bits.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, this value is described
in 12 bits with bits 3-0 of the Extended Vertical Sync Start Register (CR32) supplying the 4 most
significant bits.
This 10-bit or 12-bit value should equal the vertical sync start in terms of the number of scanlines
from the beginning of the active display area to the beginning of the vertical sync pulse. Since the
active display area always starts on the 0th scanline, this number should be equal to the number of
the scanline on which the vertical sync pulse begins minus 1.
69000 Databook
Vertical Sync Start Register
6
5
Subject to Change Without Notice
CRT Controller Registers
Vertical Sync Start Bits 7-0
4
3
2
Revision 1.3 8/31/98
1
0