M69000 Asiliant Technologies, M69000 Datasheet - Page 183

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

14-16
XR61
read/write at I/O address 3D7h with index at I/O address 3D6h set to 61h
7
6
5
4
3
2
1
0
&+,36
Reserved
(0)
7
Reserved
This bit always has the value of 0 when read.
DPMS VSYNC Output Select 2
0: The value carried by bit 2 of this register is output on the VSYNC pin. This is the default after
reset.
1: The internal power sequencing clock is output on the VSYNC pin.
DPMS HSYNC Output Select 2
0: The value carried by bit 0 of this register is output on the HSYNC pin. This is the default after
reset.
1: The internal power sequencing clock is output on the HSYNC pin.
DPMS HSYNC/VSYNC State Control
0: HSYNC and VSYNC pins are tri-stated during standby or panel-off modes. This is the default
after reset.
1: HSYNC and VSYNC pins are driven during standby or panel-off modes with whatever data or
signals that are selected by the other bits in this register.
DPMS VSYNC Output Select 1
0: The VSYNC signal is output on the VSYNC pin. This is the default after reset.
1: Bit 6 of this register is used to select what is output on the VSYNC pin.
DPMS VSYNC Output Data
The value to which this bit is set is output on the VSYNC pin if bits 6 and 3 of this register are set
to 0 and 1, respectively.
DPMS HSYNC Output Select 1
0: The HSYNC signal is output on the HSYNC pin. This is the default after reset.
1: Bit 5 of this register is used to select what is output on the HSYNC pin.
DPMS HSYNC Output Data
The value to which this bit is set is output on the HSYNC pin if bits 5 and 1 of this register are set
to 0 and 1, respectively.
69000 Databook
DPMS Sync Control Register
VSYNC
DPMS
(0)
6
HSYNC
DPMS
(0)
5
Subject to Change Without Notice
DPMS State
Extension Registers
Control
(0)
4
VSYNC Sel
DPMS
(0)
3
VSYNC Data
DPMS
(0)
2
HSYNC Sel
DPMS
(0)
Revision 1.3 8/31/98
1
HSYNC Data
DPMS
(0)
0