M69000 Asiliant Technologies, M69000 Datasheet - Page 84
M69000
Manufacturer Part Number
M69000
Description
Manufacturer
Asiliant Technologies
Datasheet
1.M69000.pdf
(360 pages)
Specifications of M69000
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7-12
INTLINE
read/write at PCI configuration offset 3Ch
byte accessible
accessible only via PCI configuration cycles
7-0
INTPIN
read-only at PCI configuration offset 3Dh
byte accessible
accessible only via PCI configuration cycles
7-0
&+,36
7
7
Interrupt Line
This register carries the level number of the interrupt line to which the interrupt output is routed by
the host system. The graphics controller does not use the information in this register. The data is
normally written to with the value determined by the host system’s POST code, and then later read
by other software to find out which interrupt level on the host CPU should be ‘hooked’ by interrupt
software.
Sub-class Code
This register always returns a value of01h to indicate that the interrupt output should be connected
to the INTA# signal.
69000 Databook
Interrupt Pin Register
Interrupt Line Register
6
6
5
5
Subject to Change Without Notice
PCI Configuration Registers
4
4
Interrupt Line
Interrupt pin
(00h)
(01h)
3
3
2
2
Revision 1.3 8/31/98
1
1
0
0
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