M69000 Asiliant Technologies, M69000 Datasheet - Page 138

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

SR01
read/write at I/O address 3C5h with index at address 3C4h set to 01h
7-6
5
4
3
2
1
0
&+,36
7
Reserved
Screen Off
0: Permits normal operation
1: Disables all graphics output except for video playback windows and turns off the picture-
generating logic allowing the full memory bandwidth to be available for both host CPU accesses
and accesses by the multimedia engine for video capture and playback functions. Synchronization
pulses to the display, however, are maintained. Setting this bit to 1 can be used as a way to more
rapidly update the frame buffer.
Shift 4
0: Causes the video data shift registers to be loaded every 1 or 2 character clock cycles, depending
on bit 2 of this register.
1: Causes the video data shift registers to be loaded every 4 character clock cycles.
Dot Clock Divide
Setting this bit to 1 divides the dot clock by two and stretches all timing periods. This bit is used in
standard VGA 40-column text modes to stretch timings to create horizontal resolutions of either 320
or 360 pixels as opposed to 640 or 720 pixels, normally used in standard VGA 80-column text
modes.
0: Pixel clock is left unaltered.
1: Pixel clock is divided by 2.
Shift Load
This bit is ignored if bit 4 of this register is set to 1.
0: Causes the video data shift registers to be loaded on every character clock, if bit 4 of this register
is set to 0.
1: Causes the video data shift registers to be loaded every 2 character clocks, provided that bit 4
of this register is set to 0.
Reserved
8/9 Dot Clocks
0: Selects 9 dot clocks (9 horizontal pixels) per character in text modes with a horizontal resolution
of 720 pixels
1: Selects 8 dot clocks (8 horizontal pixels) per character in text modes with a horizontal resolution
of 640 pixels
Reserved
69000 Databook
Clocking Mode Register
6
Screen Off
5
Subject to Change Without Notice
Sequencer Registers
Shift 4
4
Dot Clock
Divide
3
Shift Load
2
Reserved
Revision 1.3 8/31/98
1
8/9 Dot
Clocks
0
10-3