M69000 Asiliant Technologies, M69000 Datasheet - Page 149

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

11-6
GR05
read/write at I/O address 3CFh with index at address 3CEh set to 05h
7
6-5
&+,36
Reserved
7
Reserved
Shift Register Control
In standard VGA modes, pixel data is transferred from the 4 graphics memory planes to the palette
via a set of 4 serial output bits. These 2 bits of this register control the format in which data in the
4 memory planes is serialized for these transfers to the palette.
0, 0: One bit of data at a time from parallel bytes in each of the 4 memory planes is transferred to
the palette via the 4 serial output bits, with 1 of each of the serial output bits corresponding to a
memory plane. This provides a 4-bit value on each transfer for 1 pixel, making possible a choice
of 1 of 16 colors per pixel.
0, 1: Two bits of data at a time from parallel bytes in each of the 4 memory planes are transferred
to the palette in a pattern that alternates per byte between memory planes 0 and 2, and memory
planes 1 and 3. First the even-numbered and odd-numbered bits of a byte in memory plane 0 are
transferred via serial output bits 0 and 1, respectively, while the even-numbered and odd-numbered
bits of a byte in memory plane 2 are transferred via serial output bits 2 and 3. Next, the even-
numbered and odd-numbered bits of a byte in memory plane 1 are transferred via serial output bits
0 and 1, respectively, while the even-numbered and odd-numbered bits of memory plane 3 are
transferred via serial out bits 1 and 3. This provides a pair of 2-bit values (one 2-bit value for each
of 2 pixels) on each transfer, making possible a choice of 1 of 4 colors per pixel.
69000 Databook
Graphics Mode Register
This alternating pattern is meant to accommodate the use of the Odd/Even mode of
organizing the 4 memory planes, which is used by standard VGA modes 2h and 3h.
Shift Register Control
Serial Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer
Serial Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer
6
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
plane 3
plane 2
plane 1
plane 0
plane 2
plane 2
plane 0
plane 0
bit 7
bit 7
bit 6
bit 7
bit 6
bit 7
bit 7
bit 7
5
Subject to Change Without Notice
Graphics Controller Registers
plane 3
plane 2
plane 1
plane 0
plane 2
plane 2
plane 0
plane 0
bit 6
bit 6
bit 5
bit 4
bit 5
bit 4
bit 6
bit 6
Even
Odd/
4
plane 3
plane 2
plane 1
plane 0
plane 2
plane 2
plane 0
plane 0
bit 5
bit 5
bit 5
bit 5
bit 3
bit 2
bit 3
bit 2
Read Mode
plane 3
plane 2
plane 1
plane 0
plane 2
plane 2
plane 0
plane 0
bit 4
bit 4
bit 4
bit 4
bit 1
bit 0
bit 1
bit 0
3
plane 3
plane 2
plane 1
plane 0
plane 3
plane 3
plane 1
plane 1
bit 3
bit 3
bit 3
bit 3
bit 7
bit 6
bit 7
bit 6
Reserved
2
plane 3
plane 2
plane 1
plane 0
plane 3
plane 3
plane 1
plane 1
bit 2
bit 2
bit 2
bit 2
bit 5
bit 4
bit 5
bit 4
plane 3
plane 2
plane 1
plane 0
bit 1
bit 1
bit 1
bit 1
plane 3
plane 3
plane 1
plane 1
bit 3
bit 2
bit 3
bit 2
Revision 1.3 8/31/98
1
Write Mode
plane 3
plane 2
plane 1
plane 0
bit 0
bit 0
bit 0
bit 0
plane 3
plane 3
plane 1
plane 1
bit 1
bit 0
bit 1
bit 0
0