M69000 Asiliant Technologies, M69000 Datasheet - Page 238

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

FR1F
read/write at I/O address 3D1h with index at I/O address 3D0h set to 1Fh
7-6
5-4
3
2
1
0
&+,36
7
Reserved. The BIOS must program this bit to a 1.
Pixel Data Pin Diagnostic Output Mode
These bits control the output of pins: SHFCLK, LP, M, P bits 15-0 and CA bits 7-0.
00: Normal Operation (default)
01: Output the following internal signals:
Signal
PDCLK
RDDE
RDBLANK
RDVIDEO bits 23-16
RDVIDEO bits 15-0
10: Output the following internal signals on P bits 15-0
PDDELETE, PDGDCK, PHHSTR[2:0], PHREMAIN bits 10-0
11: Output the following internal signals on P bits 13-0
SS1ROMBOE, FHC32KHZI, FHXMEMRQ, T2DDSPBP, T2DDSPEN, T2DHBLANK, MXSQRDBG bits 7-0
FP Miscellaneous module control 2
0: Normal Operation. This is the default after reset.
1: Enable the ring oscillator. The waveform is output on ACTI pin. In addition, it is also output on
pin A25 if the configuration option of pin AA4 is chosen to output clocks on A24 and A25.
FP Miscellaneous module control 2
0: Normal Operation. This is the default after reset.
1: Bypass clock divider for testing purposes.
Bypass VGA Palette
0: Normal Operation. This is the default after reset.
1: Bypass internal VGA palette.
FP Interface Diagnostic Mode
0: Normal Operation. This is the default after reset.
1: FP Interface Diagnostic Mode
Reserved
69000 Databook
(00)
Diagnostic Register
6
5
Pins
FLM
LP
M
CA bits 7-0
P bits 15-0
Output Mode
Pixel Data
Subject to Change Without Notice
(00)
Flat Panel Registers
4
Misc Mod
Control 2
(0)
3
Misc Mod
Control 2
(0)
2
Bypass VGA
Palette
(0)
Revision 1.3 8/31/98
1
Diagnostic
Mode
(0)
0
15-23