M69000 Asiliant Technologies, M69000 Datasheet - Page 121

• Manufacturer Part Number: M69000
• Manufacturer: Asiliant Technologies

Specifications of M69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9-28
CR18
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 18h
7-0
CR22
read-only at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 22h
7-0
&+,36
7
7
Line Compare Bits 7-0
Memory Read Latch Data
This register provides the value currently stored in 1 of the 4 memory read latches. Bits 1 and 0 of
the Read Map Select Register (GR04) select which of the 4 memory read latches may be read using
this register.
69000 Databook
Line Compare Register
Memory Read Latch Data Register
This register provides the 8 least significant bits of a 10-bit value that specifies the scanline
at which the memory address counter restarts at the value of 0. Bit 6 of the Maximum
Scanline Register (CR09) supplies the most significant bit, and bit 4 of the Overflow
Register (CR07) supplies the second most significant bit.
Normally, this 10-bit value is set to specify a scanline after the last scanline of the active
display area. When this 10-bit value is set to specify a scanline within the active display
area, it causes that scanline and all subsequent scanlines in the active display area to
display video data starting at the very first byte of the frame buffer. The result is what
appears to be a screen split into a top and bottom part, with the image in the top part being
repeated in the bottom part.
When used in cooperation with the Start Address High Register (CR0C) and the Start
Address Low Register (CR0D), it is possible to create a split display, as described earlier,
but with the top and bottom parts displaying different data. The top part will display
whatever data exists in the frame buffer starting at the address specified in the two start
address registers (CR0C and CR0D), while the bottom part will display whatever data
exists in the frame buffer starting at the first byte of the frame buffer.
6
6
5
5
Subject to Change Without Notice
CRT Controller Registers
Memory Read Latch Data
Line Compare Bits 7-0
4
4
3
3
2
2
Revision 1.3 8/31/98
1
1
0
0