TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 228
TSI148-133IL
Manufacturer Part Number
TSI148-133IL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets
1.TSI148-133CL.pdf
(391 pages)
2.TSI148-133CL.pdf
(2 pages)
3.TSI148-133CL.pdf
(12 pages)
Specifications of TSI148-133IL
Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
800-1905
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10. Registers > Register Map
228
MOST (Maximum Outstanding Split Transactions): Three outstanding split transactions
are supported. Changing the value of this field decreases the maximum number of outstanding
split transactions:
Table 52: MOST Encoding
MMRBC (Maximum Memory Read Byte Count): This field sets the maximum byte count
the device uses when initiating a read sequence with one of the burst memory commands:
Table 53: MMRBC Encoding
ERO (Enable Relaxed Ordering): The Tsi148 does not support relaxed ordering. When this
field is read, the value is always zero.
DPERE (Data Parity Recovery Enable): When this bit is set and the device is in PCI-X
mode, the Tsi148 does not assert SERR_ when the master data parity error bit is set. When
this bit is clear and the device is in PCI-X mode, the Tsi148 asserts SERR_ when the master
data parity error bit is set.
NCAPP (Next Capabilities Pointer): This field points to the next item in the Capabilities
List. A zero indicates that this is the final item in the list.
CAPID (Capabilities ID): This field defines this item in the capabilities list as a PCI-X
register set. When this field is read, the value is always 0x07.
MMRBC
011b - 111b
00b
01b
10b
11b
MOST
000b
001b
010b
Byte Count
1024
2048
4096
512
Maximum Outstanding
1
2
3
3
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
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