TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 320
TSI148-133IL
Manufacturer Part Number
TSI148-133IL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets
1.TSI148-133CL.pdf
(391 pages)
2.TSI148-133CL.pdf
(2 pages)
3.TSI148-133CL.pdf
(12 pages)
Specifications of TSI148-133IL
Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
800-1905
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10. Registers > Register Map
Interrupt Enable Clear Register
320
Bits
7:0
9
8
SYSFLC
Reserved
ACFLC
DMA1C (DMA 1 Interrupt Clear): When this bit is set, the DMA 1 controller interrupt is
cleared. This bit always reads zero and writing a zero has no effect.
DMA0C (DMA 0 Interrupt Clear): When this bit is set, the DMA 0 controller interrupt is
cleared. This bit always reads zero and writing a zero has no effect.
LM3C (Location Monitor 3 Interrupt Clear): When this bit is set, the location monitor 3
interrupt is cleared. This bit always reads zero and writing a zero has no effect.
LM2C (Location Monitor 2 Interrupt Clear): When this bit is set, the location monitor 2
interrupt is cleared. This bit always reads zero and writing a zero has no effect.
LM1C (Location Monitor 1 Interrupt Clear): When this bit is set, the location monitor 1
interrupt is cleared. This bit always reads zero and writing a zero has no effect.
LM0C (Location Monitor 0 Interrupt Clear): When this bit is set, the location monitor 0
interrupt is cleared. This bit always reads zero and writing a zero has no effect.
MB3C (Mail Box 3 Interrupt Clear): When this bit is set, the mail box 3 interrupt is cleared.
This bit always reads zero and writing a zero has no effect.
MB2C (Mail Box 2 Interrupt Clear): When this bit is set, the mail box 2 interrupt is cleared.
This bit always reads zero and writing a zero has no effect.
MB1C (Mail Box 1 Interrupt Clear): When this bit is set, the mail box 1 interrupt is cleared.
This bit always reads zero and writing a zero has no effect.
MB0C (Mail Box 0 Interrupt Clear): When this bit is set, the mail box 0 interrupt is cleared.
This bit always reads zero and writing a zero has no effect.
PERRC (PCI/X Bus Error Interrupt Clear): When this bit is set, the PCI/X bus error
interrupt is cleared. This bit always reads zero and writing a zero has no effect.
VERRC (VMEbus Error Interrupt Clear): When this bit is set, the VMEbus error interrupt
is cleared. This bit always reads zero and writing a zero has no effect.
Name
System Fail Interrupt Clear
AC Fail Interrupt Clear
N/A
Function
Tsi148 PCI/X-to-VME Bus Bridge User Manual
PCFS
Space
Type
C
R
C
Reset
80A3020_MA001_13
N/A
By
-
-
Reset
Value
0x00
0x00
0x00
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