TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 307

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
IRQ2F (IRQ2 Function): These bits define the function of the VMEbus IRQ[2]O signal line
as an output.
Table 128: VMEbus IRQ[2]O Function
BIP (Broadcast Interrupt Pulse): When the broadcast interrupt pulse mode is enabled,
setting this bit causes a pulse to be generated on the VMEbus IRQ[1]O or IRQ[2]O signal
line. This bit always reads zero and writing a zero has no effect.
BIPS (Broadcast Interrupt Pulse Status): When this bit is high, the broadcast interrupt
pulse is still being generated by the pulse generator. When this bit is low, the pulse generator
has finished generating the broadcast interrupt pulse. This is a read only status bit.
IRQC (VMEbus IRQ Clear): When this bit is set high, the IRQL bits are reset and the
VMEbus interrupt is removed. This bit should only be used to recover from an error
condition. Normally VMEbus interrupts should not be removed. This bit always reads zero
and writing a zero has no effect.
IRQLS (VMEbus IRQ Level Status): These bits are read-only status bits and they define the
current level of a pending VMEbus interrupt.
IRQS (VMEbus IRQ Status): When this bit is high, the VMEbus interrupt has not been
acknowledged. When this bit is low, the VMEbus interrupt has been acknowledged. This is a
read only status bit.
IRQL (VMEbus IRQ Level): These bits define the level of the VMEbus interrupt generated
by the Tsi148. A VMEbus interrupt is generated by writing the desired level to these bits.
These bits always read 0 and writing a 0 to these bits has no effect. These bits are
automatically cleared following the VMEbus interrupt acknowledge cycle.
STID (STATUS/ID): These bits define the VMEbus vector that is returned during an
interrupt acknowledge cycle.
IRQ2F
00b
01b
10b
11b
VMEbus IRQ[2]O Function
Programmable Clock
Pulse Generator
1.02 s Clock
Normal
10. Registers > Register Map
307