TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 62

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

2. VME Interface > VME Master
2.3.6.2
62
The processor sends an interrupt by reading or writing one to the VMEbus monitored address.
The other boards in the system monitor this address and interrupt their processors when an
access is detected. There are four locations which are monitored and each location is eight
bytes. VMEbus address bits 3 and 4 are used to define the specific location.
relationship between the VMEbus address and the location monitor interrupt.
Table 2: Location Monitor Interrupt Addresses
When the location monitor detects an access to one of the locations being monitored, an
interrupt is sent to the interrupter. If the interrupt is enabled, then the selected INTx signal is
asserted. The status of the interrupt is available in the Global Control and Status (GCSR)
registers (see
Section 10.2.3 on page
No data is transferred during a Location Monitor access. The slave boards monitoring the
location do not respond. The board generating the location monitor cycle is responsible for
terminating the VMEbus cycle with a DTACK* signal. The board generating a location
monitor cycle must have its location monitor enabled and programmed to monitor the location
monitor address.
Semaphore Registers
The GCSR registers include eight semaphore registers. These semaphore registers can be
used to allow processes running on the local processor and processes running on processors
on other VMEbus boards to share resources. Each semaphore register is 8-bits and there are
four semaphore registers in a 32-bit register. The most significant bit (bit 7) is the semaphore
bit and the remaining seven bits (bits 6 to 0) are the tag field.
To gain ownership of the semaphore, a process writes to the semaphore with bit 7 set and a
unique code in the tag field. The process has gained ownership if a subsequent read returns
the unique code. The process releases the semaphore by setting the semaphore register to 0.
A semaphore register is only updated when bit 7 in the register is zero and a one is written to
bit 7 of the register, or when a zero is written to bit 7.
VMEbus Address
LMBA + (10-17)
LMBA + (18-1F)
LMBA + (0-7)
LMBA + (8-F)
Section 10.2.4 on page
193).
Location Monitor
193) and Local Control and Status (LCSR) registers (see
Interrupt
LM0
LM1
LM2
LM3
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Table 2
shows the