TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 8
TSI148-133IL
Manufacturer Part Number
TSI148-133IL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets
1.TSI148-133CL.pdf
(391 pages)
2.TSI148-133CL.pdf
(2 pages)
3.TSI148-133CL.pdf
(12 pages)
Specifications of TSI148-133IL
Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
800-1905
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TSI148-133IL
Manufacturer:
IDT
Quantity:
47
Company:
Part Number:
TSI148-133IL
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
TSI148-133ILY
Manufacturer:
SUMPLUS
Quantity:
210
Company:
Part Number:
TSI148-133ILY
Manufacturer:
IDT
Quantity:
201
- Current page: 8 of 391
- Download datasheet (2Mb)
Contents
8
10.4.47 Inbound Translation Starting Address Lower (0-7) Registers . . . . . . . . . . . . . . . . . . . 278
10.4.48 Inbound Translation Ending Address Upper (0-7) Registers . . . . . . . . . . . . . . . . . . . . 279
10.4.49 Inbound Translation Ending Address Lower (0-7) Registers. . . . . . . . . . . . . . . . . . . . 280
10.4.50 Inbound Translation Offset Upper (0-7) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
10.4.51 Inbound Translation Offset Lower (0-7) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
10.4.52 Inbound Translation Attribute (0-7) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
10.4.53 GCSR Base Address Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
10.4.54 GCSR Base Address Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
10.4.55 GCSR Attribute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
10.4.56 CRG Base Address Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
10.4.57 CRG Base Address Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.4.58 CRG Attribute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.4.59 CR/CSR Offset Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
10.4.60 CR/CSR Offset Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.4.61 CR/CSR Attribute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
10.4.62 Location Monitor Base Address Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
10.4.63 Location Monitor Base Address Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
10.4.64 Location Monitor Attribute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
10.4.65 64-bit Counter Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
10.4.66 64-bit Counter Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
10.4.67 Broadcast Pulse Generator Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
10.4.68 Broadcast Programmable Clock Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
10.4.69 VMEbus Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
10.4.70 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
10.4.71 Interrupt Enable Out Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
10.4.72 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.4.73 Interrupt Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
10.4.74 Interrupt Map 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
10.4.75 Interrupt Map 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
10.4.76 DMA Control (0-1) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
10.4.77 DMA Status (0-1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
10.4.78 DMA Current Source Address Upper (0-1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . 335
10.4.79 DMA Current Source Address Lower (0-1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . 336
10.4.80 DMA Current Destination Address Upper (0-1) Registers . . . . . . . . . . . . . . . . . . . . . 337
10.4.81 DMA Current Destination Address Lower (0-1) Registers . . . . . . . . . . . . . . . . . . . . . 338
10.4.82 DMA Current Link Address Upper (0-1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
10.4.83 DMA Current Link Address Lower (0-1) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
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