TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 30

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

1. Functional Overview > VMEbus Interface
1.2
1.2.1
1.2.2
30
VMEbus Interface
The Tsi148 VMEbus Interface is compliant with the following standards:
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•
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For more information on the VME Interface refer to
2eVME Protocol
The 2eVME protocol doubles the VME64 peak block data rate to 160 Mbytes/s by utilizing
both edges of the DS* signal and the DTACK signal to validate data. The addressing phase of
the transaction also differs from VME64 transactions because the address broadcast is split
into three phases. The three phase address broadcast transmits extended AM codes
(programmable limit of 256 codes), VME master information, and the transaction beat count.
The 2eVME protocol doubles peak block data rate and has flexibility in transaction
terminations. The following terminations of transactions are allowed in 2eVME:
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•
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Refer to the American National Standard for VME64 Extensions for more information on the
2eVME protocol.
2eSST Protocol
The 2eSST protocol further increases VME transaction bandwidth with programmable
transfer rates of 160, 267, and 320 Mbytes/s.
Although the 2eSST protocol is similar to the 2eVME protocol there are a number of
differences and specific requirements for 2eSST protocol. Transactions are source
synchronous in 2eSST; there is no acknowledgement from receiver of the data. This lack of
acknowledgement enables transactions to happen at a faster rate; there are no delays caused
by multiple acknowledgments as in the original VME standard.
Performance enhancements delivered by 2eSST require careful management of system-wide
skew. 2eSST protocol implementation is possible on standard VME64x five row backplanes
with Texas Instrument’s high performance bus transceivers
American National Standard for VME64 (ANSI/VITA 1.0 - 1994 (R2002))
American National Standard for VME64 Extensions (ANSI/VITA 1.1 - 1997)
Source Synchronous Transfer (2eSST) Standard
Master termination: Before the beat count expires
Slave terminated transactions: Using the RETRY* and BERR* signals
Slave suspended terminations: Using the RETRY* and DTACK* signals
Tsi148 PCI/X-to-VME Bus Bridge User Manual
Section 2. on page
43.
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